What is close loop and open loop in controls, what are the differences and what are their similarities. Please illustrate using a block diagram if possible

Design and simulate a Half and Full wave rectifier for a 12V AC supply with 60 Hz frequency.

Please use online multisim

and calculation

I am trying to write the code for an 8 bit adder in VHDL so that I can program it onto my Elbert V2 Spartan 3A FPGA Development Board, but I keep getting errors. Any ideas what I am doing wrong?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder8bit is
Port ( a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
cin : in STD_LOGIC;
o : out STD_LOGIC_VECTOR(7 downto 0);
cout : out STD_LOGIC);
end adder8bit;

architecture Behavioral of adder8bit is

component fulladder is
   Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
o : out STD_LOGIC;
cout : out STD_LOGIC
);
end component;

signal c : STD_LOGIC_VECTOR(6 downto 0);

begin

PROCESS (a,b,cin)
BEGIN

o(0) <= a(0) xor b(0) xor cin;
c(0) <= (cin and b(0)) or (cin and a(0)) or (a(0) and b(0));

for i in 1 to 7 loop

o(i) <= a(i) xor b(i) xor c(i-1);
c(i) <= (c(i-1) and b(i)) or (c(i-1) and a(i)) or (a(i) and b(i));

end loop;

cout <= c(6);

END PROCESS;

end Behavioral;

An AC power supply is in series with a 30 μF capacitor and a parallel structure with a 100 Ω resistor and a 300 mH inductor. The power supply produces electricity at frequency of 60 cycles / second with an RMS voltage of 120.0 V.

a) What is the formula (including appropriate units) for function of the voltage of the power supply (w.r.t. time when time is in seconds) assuming the voltage was started at its maximum positive value?

b) Draw the full phasor diagram when the resistance voltage phasor is at π/6 . Include identifying angles for the 8 phasors ( ε_0,V_r ,V_c ,V_L ,I_p ,I_r ,I_c ,I_L ).

c) What are the equations for the voltages across and currents into each component? (There are 8 equations in all.)

d) Assume the voltage from the power supply starts at its maximum positive value, what is first time when resistance voltage phasor is at π/6 ?

e) At that moment in part (d), what are the instantaneous voltages across each of the four components, and what are the instantaneous currents into each of the four components?

A string of 6 suspension insulators is to be fitted with guard ring. The pin to earth capacitances are equal to C. what are the values of line to pin capacitances to have uniform distribution over the string ?

explain how a capacitor stores energy as an electrostatic charge. also draw a couple pictures

Draw the circuit of a Boost Regulator and explain the operation of this circuit with the aid of waveforms.

Question 41

1. The 802.11 standard specifies the use of what technique in order to minimize the potential for collisions?

   	a.	Carrier Sense Multiple Access with Collision Detection (CSMA/CD)
   	b.	Carrier Sense Single Access with Collision Adaptation (CSSA/CA)
   	c.	Carrier Sense Multiple Access with Collision Mitigation (CMSA/CM)
   	d.	Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA)

1.25 points

Question 42

1. The LLC sublayer is primarily concerned with managing MAC addresses in message frames.

   True

   False

1.25 points

Question 43

1. The ST and SC fiber connectors are the most commonly found connectors due to their smaller sizes.

   True

   False

1.25 points

Question 44

1. The Wi-Fi Protected Setup PIN can be easily cracked through a brute force attack.

   True

   False

1.25 points

Question 45

1. The Wireless Personal Area Network (WPAN) is defined in the 802.15 standard.

   True

   False

1.25 points

Question 46

1. The most secure Wi-Fi communication is made possible by combining a RADIUS server with WPA or WPA2, known as WPA-Enterprise or WPA2-Enterprise, respectively.

   True

   False

1.25 points

Question 47

1. The use of multiple antennas on an access point to issue a signal to one or more receivers is enabled by what 802.11 innovation?

   	a.	channel bonding
   	b.	multiple input-multiple output (MIMO)
   	c.	spread spectrum frequency hopping
   	d.	frame aggregation

1.25 points

Question 48

1. The wireless spectrum, as defined by the FCC, spans between which two frequencies?

   	a.	3 kHz and 500 GHz
   	b.	9 kHz and 300 GHz
   	c.	125 kHz and 150 GHz
   	d.	3 MHz and 300 GHz

1.25 points

Question 49

1. Upon connecting to a Wi-Fi network, you're redirected to a login screen and a request to accept terms of service before being connected. What is this an example of?

   	a.	captive portal
   	b.	guest network profile
   	c.	WPA2-Enterprise
   	d.	browser hijacking

1.25 points

Question 50

1. Utilizing time slots that are adjusted according to priority and need is an example of what type of multiplexing on copper lines?

   	a.	frequency division multiplexing
   	b.	time division multiplexing
   	c.	statistical time division multiplexing
   	d.	wavelength division multiplexing

1.25 points

Question 51

1. What 802.11 frame type is involved in association and reassociation, including probe and beacon frames?

   	a.	control frames
   	b.	extended frames
   	c.	management frames
   	d.	data frames

1.25 points

Question 52

1. What is the fastest Ethernet standard that can possibly be used on twisted-pair cabling?

   	a.	10TBase-T
   	b.	10GBase-T
   	c.	1000Base-T
   	d.	100Base-T

1.25 points

Question 53

1. What is the industry standard angle for an Angle Polished Connector (APC)?

   	a.	16 degrees
   	b.	14 degrees
   	c.	12 degrees
   	d.	8 degrees

1.25 points

Question 54

1. What is the maximum supported throughput of a CAT6 cable?

   	a.	100 Mbps
   	b.	1 Gbps
   	c.	100 Gbps
   	d.	10 Gbps

1.25 points

Question 55

1. What is the minimum category of UTP cable required in order to support Gigabit speeds?

   	a.	Cat 5
   	b.	Cat 5e
   	c.	Cat 3
   	d.	Cat 6

1.25 points

Question 56

1. What is the purpose of the Layer 2 LLC sublayer?

   	a.	It is used to manage MAC addresses in message frames.
   	b.	It is used to handle multiplexing, flow and error control, and reliability.
   	c.	It performs management of the physical layer's modulation techniques.
   	d.	It is used to manage low-level encryption on a network.

1.25 points

Question 57

1. What kind of tool can you use to measure voltage on a cable length?

   	a.	time domain reflectometer
   	b.	light meter
   	c.	multimeter
   	d.	continuity tester

1.25 points

Question 58

1. What multiplexing technology lowers cost by spacing frequency bands wider apart to allow for cheaper transceiver equipment?

   	a.	dense wavelength division multiplexing
   	b.	spaced wavelength division multiplexing
   	c.	coarse wavelength division multiplexing
   	d.	statistical time division multiplexing

1.25 points

Question 59

1. What optional protocol can be used in 802.11 to reserve the medium for one node's use?

   	a.	RTS/CTS (Request to Send/Clear to Send)
   	b.	HA/RA (Hold Airtime/Reserved Airtime)
   	c.	RAR/CTU (Reserve Airtime Request/Clear to Use)
   	d.	RT/FT (Request Time/Fair Time)

1.25 points

Question 60

1. What scenario describes an evil twin attack?

   	a.	A hacker is actively sending wireless probes to discover available wireless networks.
   	b.	A malicious access point is configured with the SSID of a non-malicious public access point.
   	c.	An attacker is actively attempting to brute force the PIN of a WPS enabled access point.
   	d.	A hacker is utilizing a protocol analyzer on a public Wi-Fi network to discover packet contents.

Logisim Evolution is a freeware

4. Bit sequence recognizer [30]

• Submission file for this part: 4.circ
• Main circuit name: sequencecheck
• Input pin(s): inputx [1], sysclock [1]
• Output pin(s): outputr [1]

Derive a minimal state table for a Mealy model FSM that acts as a sequence checker. During four consecutive clock cycles, a sequence of four values of the signal x is applied, forming a binary number. The oldest value of x would become the most significant bit in that binary number. The most recent value of x would become the least significant bit.

The FSM will output outputr = 1 when it detects that the previous 4 bit sequence was either 0100 or 1010. At all other times, including when the previous sequence was not those described previously, outputr = 0. Implement the FSM as a circuit in Logisim Evolution.

Note that much like the last problem, this is not a sliding window. After the fourth clock pulse, the circuit resets itself and is ready to take in the next 4 bit sequence.

You will lose a significant portion of credit if your FSM is not minimized.

You will lose a significant portion of credit if your combinational logic is not minimized. If you violate both this and the previous constraint, you will get a 0.

can you provide me by two questions with answers for fundamental of electrical enginnering. I want to test an expert   I want questions for testing an expert send the question with answers make it clear separat question and answer(hot question)

Implement the following logic function as embedded logic inside a positive TSPC register.

F= ab + bcd + ad

a. Find the average and rms values of the current i(t) = 6 + 10 sin ωt A.
Vb in the voltage-regulator circuit below varies by ± 10 % from its nominal value of 12 V. If the circuit has a constant reverse breakdown voltage
VZ = 8.2 V for 75 mA ≤ iZ ≤ 1 A.
b. Obtain RS that will maintain vL = VZ = 8.2 V
c. Determine iZ ≥ 75 mA at the lowest value of Vb

How to design FIR lowpass filter using matlab.

Note : Do not write matlab code. Only explain the steps of designing filter