Question

Write the VHDL codes for (7494) 4 bit shift register using Behavioral style of modeling. this is the datasheet for this Quation ( http://www.ralphselectronics.com/productimages/SEMI-SN7494N.PDF )

Answer 1

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Shift_Reg is
    port(din : in STD_LOGIC;
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        dout : out STD_LOGIC);
end Shift_Reg;
architecture of Shift_Reg is
begin
    siso : process (clk,din,reset) is
    signal s : std_logic_vector(3 downto 0) := "0000" ;
    begin
        if (reset='1') then
            s := "0000";
        else if (rising_edge (clk)) then       
            s := (din & s(3 downto 1));    
            dout <= s(0);
        end if;
    end process siso;   
end Shift_Reg;