Question

How would you design a cache coherence with only MS, not MSI. How do you manage the new protocol?

Draw the new MS protocol. For each state, show all the relevant transitions.

In the new MSI protocol, when does a memory read occur? Specify the bus transaction, the requestor's start and end states, and the states of the other caches if relevant.

In the new MSI protocol, when does a memory write occur? Specify the bus transaction and the requestor's start and end states. Specify any other scenario where a memory write occurs.

Answer 1

The MESI protocol is an Invalidate-situated cache coherence protocol, and is one of the most customary protocols which help write-back caches. It is often referred to as the Illinois protocol (because of its development at the university of Illinois at Urbana-Champaign). Write back caches can shop loads on bandwidth that's in general wasted on a write by means of cache. There's perpetually a soiled state present in write back caches which shows that the information in the cache is exclusive from that in major memory. Illinois Protocol requires cache to cache switch on a pass over if the block resides in another cache. This protocol reduces the number of main memory transactions with admire to the MSI protocol. This marks a huge improvement in the performance.
Essentially the most striking change between the two protocols is the extra "exotic" state present within the MESI protocol. This additional state used to be delivered as it had many benefits to it. In case a processor desires to learn a block which none of the other processors have and then write to it, right here two bus transactions will take place within the case of MSI. First might be a BusRd request to learn the block followed by way of a BusRdX request earlier than writing to the block. The BusRdX request in this state of affairs is vain as none of the different caches have the same block, but there is no method for one cache to learn about this. As a result, MESI protocol overcomes this hassle by means of including an unique state, which results in saving a bus request. This makes a gigantic change when a sequential application is going for walks. As just one processor might be engaged on it, all the accesses will likely be distinguished. The MSI would have carried out very badly right here. Even in the case of a highly parallel software where there may be minimal sharing of knowledge, MESI can be far faster.

The letters within the acronym MESI represent 4 distinct states that a cache line may also be marked with (encoded utilizing two extra bits):

Modified (M)
The cache line is reward only within the present cache, and is dirty - it has been modified (M state) from the value in major reminiscence. The cache is required to jot down the info again to main memory at a while at some point, earlier than allowing another learn of the (no longer legitimate) important reminiscence state. The write-again alterations the road to the Shared state(S).
Extraordinary (E)
The cache line is present most effective within the present cache, however is clean - it fits foremost reminiscence. It could be modified to the Shared state at any time, in line with a read request. On the other hand, it could be transformed to the Modified state when writing to it.
Shared (S)
indicates that this cache line could also be saved in other caches of the desktop and is smooth - it matches the fundamental reminiscence. The road may be discarded (changed to the Invalid state) at any time.
Invalid (I)
indicates that this cache line is invalid (unused).