5. What is a trap? Give an example. How does it differ from an interrupt?
6. Why does the Linux kernel handle certain interrupts in two stages: top half and bottom
half?
7. What is a context switch? What is the role of the kernel in a context switch?
8. What is the maximum number of processes in the system at any time using the following
code segment?
extern char mypath[];
for ( int i = 0; i <...
When an interrupt occurs while operating in User mode, present
the rWhen an interrupt occurs while operating in User mode,
present the return instruction of the exception handler and
describe the reason for such a 3 stage pipeline structure
When is an external interrupt recognized by the
CPU? When more than one interrupt occurs, what
approaches would you use to service them? What approaches should be
taken when an interrupt occurs within an interrupt service
routine
Consider a hypothetical microprocessor having 64-bit
instructions composed of two fields: the first 16-bits contains the
op-code and the remainder the immediate operand or an operand
address. Assume memory is organized in 32-bit words,
i.e. one r/w access can yield a maximum of 32
bits. ...
A) What happens when a software Interrupt occurs? Write
steps
briefly?
B) Differentiate between maskable and
non-maskable interrupts?
C) How are the multiplexed bus of 8086
demultiplexed?
D) Find the address range when a 2K x 8 memory is
interfaced with 8086/8088?
6. How does the mechanism by which diuresis occurs with diabetes
insipidus differ from that which
occurs in diabetes mellitus?
8. What other conditions result in polyuria and polydipsia
(pu/pd)?
9. What is ddavp and how is it administered?
Outline the process that occurs when a hardware interrupt is
generated by a disk controller. Set the context for the interrupt
disk read and describe how an interrupt handler would address the
event.
1) How does a bailment differ from a gift? 2) How does a
bailment differ from a lease? 3) Give an example of a bailment that
is not a contract. Give an example of a bailment that is a
contract.
II. Application 1 and 2 run concurrently. Whenever a timeout
interrupt occurs, the kernel switches control between the
applications. Show the order of instruction execution, assuming
application 1 is currently running. (42 pts)
Application 1
Application 2
...
instruction i
(timeout interrupt)
instruction i+1
...
instruction k
(timeout interrupt)
instruction k+1
...
instruction 0
...
instruction j
(timeout interrupt)
instruction j+1
...
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