Question

Write down the truth table fora 4-to-2 priority encoderhaving input W[3:0]and with priority levels in the decreasing order (i.e., W[0]-Highest, ....., W[3]-Least). Write down the Verilog code for implementing   the same.

plz asap fast

Answer 1

4 : 2 Encoder

4-2 Encoder is a combinational circuit that encodes the information from 4 inputs to 2 bit output code (just reverse operation of Decoder).It has 4 input lines and 2 output lines. In our case the 4 to 2 Encoder consists of four inputs W3, W2, W1 and W0 and two outputs A1 & A0. Only one of these 4 inputs can be one at any time, to get the respective binary code at the output.

Truth table

Input
W3	W2	W1	W1	A1	A0
0	0	0	1	0	0
0	0	1	0	0	1
0	1	0	0	1	0
1	0	0	0	1	1
0	0	0	0

// we create our module with name encoder_4_to_2

//it contain two variables, input variable w[3:0] and output variable a[1:0]

module encoder_4_to_2(

    input [3:0] w,

    output [1:0] a

    );

reg [1:0]a;

always @ (w)

// start the execution

begin

if(w==4'b0001)

a=2'b00;

else if(w==4'b0010)

a=2'b01;

else if(w==4'b0100)

a=2'b10;

else if(w==4'b1000)

a=2'b11;

else

a=2'bzz;

end

//in the first case the if the last bit is 1; then the out put will be 00
//in the first case the if the last bit is 1; then the out put will be 00
//in the second case the if the second bit is 1; then the out put will be 10

//in the second case the if the second first bit is 1; then the out put will be 11

//other wise default value will be inserted in our case ,zz will be the output