Question

1. How does the built-in RS latch in the miscellaneous digital parts bin differ from the NAND gate circuit in E6A-1.MS7?

2. Do the type-D and JK flip flops respond to the same clock edge?

3. Explain how toggle mode is the same as division by two.

4. What is the difference between a synchronous input (D, J, or K) and an asynchronous input (PR or CLR)?

Answer 1

1.

A latch (also called a flip-flop) is a fundamental component of data storage. A single latch can hold 1-bit of data, increase that number by many orders of magnitude and you can create kilo-, mega-, giga-, even tera-bytes of memory. Of course, like most digital circuits, latches are made out of digital logic gates!

There are many different kinds of latches, all with somewhat cryptic names like SR, D, JK, and T. The SR-latch is one of the most fundamental forms of a latch.

SR latch can be a combination of NOR gates or NAND gates.

The particular NAND gated circuit you mentioned is not specified here.

2.

Yes they can respond to the same clock edge i.e. they both can respond to positive edge triggering or negative edge triggering clock. Because the internal circuit of these two flip-flops is different but the response to the clock is same for both the flip-flops.

With a slight modification to a standard JK flip-flop, we can construct a new type of flip-flop called a Toggle flip-flop.

Toggle flip flops can be made from D-type flip-flops or from standard JK flip-flops such as the 74LS73. The result is a device with only two inputs, the “Toggle” input itself and the negative controlling “Clock” input.

It can be seen from the frequency waveforms of D FF that the output from Q to the input terminal D, the output pulses at Q have a frequency that are exactly one half ( f ÷ 2 ) that of the input clock frequency. In other words the circuit produces Frequency Division as it now divides the input frequency by a factor of two (an octave).

As we know the D flip flop is frequency divider by 2, the T FF which is the slight modification of D or JK FF is also a frequnecy divider by two.

3.

A “Toggle flip-flop” gets its name from the fact that the flip-flop has the ability to toggle or switch between its two different states, the “toggle state” and the “memory state”. Since there are only two states, a T-type flip-flop is ideal for use in frequency division and binary counter design.

The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs because they have effect on the outputs (Q and not-Q) only in step, or in sync, with the clock signal transitions. Another extra inputs are called asynchronous because they can set or reset the flip-flop regardless of the status of the clock signal. Typically, they’re called preset and clear:

When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the synchronous inputs or the clock. When the clear input is activated, the flip-flop will be reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock. So, what happens if both preset and clear inputs are activated? Surprise, surprise: we get an invalid state on the output, where Q and not-Q go to the same state, the same as the S-R latch! Preset and clear inputs find use when multiple flip-flops are ganged together to perform a function on a multi-bit binary word, and a single line is needed to set or reset them all at once.

Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or active-low. If they’re active-low, there will be an inverting bubble at that input lead on the block symbol, just like the negative edge-trigger clock inputs.