Question

I need a design of Up/Down Logic Counter

Brief information about the techniques to be used in the experiment will be given.

The stages of the design problem and what will be done in these stages will be specified. (state diagram, state tables, state assignments, output and state equations, implementation with gates and flip flops and so on.)

Material equipment list to be used in the implementation of the experiment will be provided.

In the section where the test result will be explained, the student will be asked to comment on the results of the experiment.

Answer 1

SYNCHRONOUS COUNTER DESIGN STEPS/PROCEDURES

1. Determine the # of FFs needed to support the counting sequence’s

highest #.

2n -1 ≥ Highest #

2. Build a State Transition Diagram. Be sure to include all states.

3. Build a State/Excitation Truth Table.

4. Simplify expressions for J and K inputs for each F/F on K-Maps.

5. Implement the Synchronous Counter/State Machine Circuit.

6. Draw the Timing Diagram (If Needed).

Bidirectional Counter

Both Synchronous and Asynchronous counters are capable of counting “Up” or counting “Down”, but their is another more “Universal” type of counter that can count in both directions either Up or Down depending on the state of their input control pin and these are known as Bidirectional Counters.

Bidirectional counters, also known as Up/Down counters, are capable of counting in either direction through any given count sequence and they can be reversed at any point within their count sequence by using an additional control input as shown below.

Synchronous 3-bit Up/Down Counter

The circuit above is of a simple 3-bit Up/Down synchronous counter using JK flip-flops configured to operate as toggle or T-type flip-flops giving a maximum count of zero (000) to seven (111) and back to zero again. Then the 3-Bit counter advances upward in sequence (0,1,2,3,4,5,6,7) or downwards in reverse sequence (7,6,5,4,3,2,1,0).

Generally most bidirectional counter chips can be made to change their count direction either up or down at any point within their counting sequence. This is achieved by using an additional input pin which determines the direction of the count, either Up or Down and the timing diagram gives an example of the counters operation as this Up/Down input changes state.

Nowadays, both up and down counters are incorporated into single IC that is fully programmable to count in both an “Up” and a “Down” direction from any preset value producing a complete Bidirectional Counter chip. Common chips available are the 74HC190 4-bit BCD decade Up/Down counter, the 74F569 is a fully synchronous Up/Down binary counter and the CMOS 4029 4-bit Synchronous Up/Down counter.

Asynchronous up/down counter

As we know that in the up-counter each flip-flop is triggered by the normal output of the preceding flip-flop (from output Q of first flip-flop to clock of next flip-flop); whereas in a down-counter, each flip-flop is triggered by the complement output of the preceding flip-flop (from output Q^ of first flip-flop to clock of next flip-flop).Here you will see in bellow diagram of 3-bit up down counter.

up down counter

The operation of such a counter is controlled by the up-down control input. Now question is in which sequence it will count see below the table for the counting sequence of the up down counter in the two modes of counting.

up down counter

As I discussed earlier that for up down counting operation preceding flip-flop sometime it need input from output from output Q of first flip-flop to clock of next flip-flop for up-counting and sometimes from output Q^ of first flip-flop to clock of next flip-flop for down-counting. So in above circuit diagram it is shown clearly. As we know a flip-flop can hold single bit so for 3 bit operation it need three flip-flops. An inverter has been inserted in between the count-up control line and the count-down control line to ensure that the count-up and count-down cannot be simultaneously in the HIGH state.

When the count-up/down line is held HIGH, the lower AND gates will be disabled and their outputs will be zero. So they will not affect the outputs of the OR gates. At the same time the upper AND gates will be enabled. Hence, QA will pass through the OR gate and into the clock input of the B flip-flop. Similarly, QB will be gated into the clock input of the C flip-flop. Thus, as the input pulses are applied, the counter will count up and follow a natural binary counting sequence from 000 to 111.

Similarly, with count-up/down line being logic 0, the upper AND gates will become disabled and the lower AND gates are enabled, allowing Q′A and Q′B to pass through the clock inputs of the following flip-flops. Hence, in this condition the counter will count in down mode, as the input pulses are applied.