Question

Derive the state diagram, state table, state assignment table, and logic network using D flip-flops for the following circuit:

A FSM has two input, w1 and w2, and an output z. The machine has to generate z=1 when the previous four values of w1 and w2 are the same; otherwise z=0. Overlapping patterns are allowed. An example of the desired behavior is:

w1: 0 1 1 0 1 1 1 0 0 0 1 1 0

w2: 1 1 1 0 1 0 1 0 0 0 1 1 1

z: 0 0 0 0 0 1 0 0 0 0 1 1 1

Answer 1