Question

mke individul modulees of for bit ader, for bit subtractor, for bit multiplier, for bit comparaator modules[You can Ignore this part]

aand theen use a multiplexxer to combine these modules to make an ALUu where user should select which operation he/she wants to perform (for instance, ALU may performs four bit addition when selection lines are ‘00’using selection lines of multiplexer or perform subtraction when selections lines are ‘01’ and so on).{Just make this}

using verilooog coding on xilinxX

answer within 1 hourrrr pleez

Answer 1

Main ALU module:-

module alu(
input [3:0] X,Y, // ALU 4-bit Inputs   
input [1:0] sel,// ALU Selection
output [3:0] result, // ALU 4-bit Output
output Carry // Carry Flag
);
reg [3:0] ALU;
reg co;
wire [3:0] Result1,Result2,Result3,Result4;
wire Carry1,Carry2,Carry3,Carry4;
add test_unit1( X,Y,Result1,Carry1);
sub test_unit2( X,Y,Result2,Carry2);
mul test_unit3( X,Y,Result3,Carry3);
comp test_unit4( X,Y,Result4,Carry4);
assign result = ALU;
assign Carry = co;
always @(*)
begin
case(sel) //Here starts the MUX logic
2'b00: // Addition
begin
ALU = Result1;
co = Carry1;
end
2'b01: // Subtraction
begin
ALU = Result2 ;
co = Carry2;
end
2'b10: // Multiplication
begin
ALU = Result3;
co = Carry3;
end
2'b11: // Comparison
begin
ALU = Result4;
co = Carry4;
end
default: ALU = X ;
endcase
end

endmodule

SUBMODULES:-

ADD MODULE:-

module add(
input [3:0] A,B, // ALU 4-bit Inputs   
output [3:0] sum, // ALU 4-bit Output
output carry // Carry Flag
);
reg [3:0] sum_alu;
wire [4:0] tmp;
assign sum = sum_alu;
assign tmp = {1'b0,A} + {1'b0,B};
assign carry = tmp[4]; // Carry flag
always @(*)
begin
sum_alu = A + B ;
end
endmodule

SUBTRACTION MODULE:-

module sub(
input [3:0] A,B, // ALU 4-bit Inputs   
output [3:0] diff, // ALU 4-bit Output
output borr // Borrow Flag
);
reg [3:0] dif_alu;
wire [4:0] tmp;
assign diff = dif_alu;
assign tmp = {1'b0,A} - {1'b0,B};
assign borr = tmp[4]; // Borrow flag
always @(*)
begin
dif_alu = A - B ;
end
endmodule

MULTIPLICATION MODULE:-

module mul(
input [3:0] A,B, // ALU 4-bit Inputs   
output [3:0] pro, // ALU 4-bit Output
output carry // Carry Flag
);
reg [3:0] mul_alu;
wire [4:0] tmp;
assign pro = mul_alu;
assign tmp = {1'b0,A} + {1'b0,B};
assign carry = tmp[4]; // Carry flag
always @(*)
begin
mul_alu = A * B ;
end
endmodule

COMPARATOR MODULE:-

module comp(
input [3:0] A,B, // ALU 4-bit Inputs   
output [3:0] com, // ALU 4-bit Output
output carry // Carry Flag
);
reg [3:0] com_alu;
assign com = com_alu;
assign carry = 1'b0; //No use of carry in this module
always @(*)
begin
com_alu = (A==B)?4'd1:4'd0 ; //if a=b is true, then com_alu=1. if a=b is false , then com_alu=0
end
endmodule

(NOTE: As you have not asked for testbench ,i have not included it.Codes are software tested and they are error free.)