Question

In: Computer Science

A computer uses direct-mapped cache with four16-bit words, and each word has an associ-ated13-bit tag. Consider...

A computer uses direct-mapped cache with four16-bit words, and each word has an associ-ated13-bit tag. Consider the following loop (three instructions) in a program. Before the loop,the values in registersR0,R1,R2are 0, 054E, and 2 respectively. Consider that instructions arealready in separate cache memory. (See Table1.)The loop starts at location LOOP=02EC.LOOPAdd(R1)+,R0;DCRR2; BR>0LOOPShow the content of cache at the end of each pass of this loop if direct mapping cache is used.Compute hit rate.

Solutions

Expert Solution

Answer:

Consider the following loop in a program where all instructions and operands are 16 bits long.

Loop Add (R1) + R0

Decrement R2

BNE LOOP

  • Assume that, before this loop is entered, registers R0, R1, and R2 contain 0, 054E, and 3, respectively.
  • Also assume that the main memory contains the data shown in Fig 1, where all entries are given in hexadecimal notation. The loop starts at location LOOP = 02EC.

  • In the rst pass through the loop, the Add instruction is stored at address 4 in the cache, and its operand (A03C) at address 6.
  • Then the operand is overwritten by the Decrement instruction.
  • The BNE instruction is stored at address 0. In the second pass, the value 05D9 overwrites the BNE instruction, then BNE is read from the main memory and again stored in location 0.
  • The contents of the cache, the number of words read from the main memory and from the cache, and the execution time for each pass are as shown below.

  • All three instructions are stored in the cache after the rst pass, and they remain in place during subsequent passes.
  • In this case, there is a total of 6 read operations from the main memory and 6 from the cache. Execution time is 66 τ .
  • Instructions and data are best stored in separate caches to avoid the data overwriting instructions.

Related Solutions

A direct mapped cache has 32 cache lines.Each cache line consists of 4 words, and each...
A direct mapped cache has 32 cache lines.Each cache line consists of 4 words, and each word is four bytes.The address bus consists of 16 bits. How many bits are required for the tag in this direct-mapped cache?
For a direct mapped cache design with 32 bit address, the following bits of the address...
For a direct mapped cache design with 32 bit address, the following bits of the address are used to access the cache Tag Index Offset 31 - 8 7 - 4 3 - 0 What is the cache block size (in words)? How many entries does the cache have? What is the ratio between total bits required for such a cache implementation over the data storage bits? Starting from power on, the following byte-addressed cache references are recorded. Address 0...
Given an 8-word, direct mapped cache, and the sequence of address accesses below, enter the number...
Given an 8-word, direct mapped cache, and the sequence of address accesses below, enter the number of misses. CACHE CONFIG 24 13 24 10 8 8 Given an 8-word, 2-way set associative cache, and the sequence of address accesses below, enter the number of misses. CACHE CONFIG 22 1 9 22 22 22 Given an 8-word, 2-way set associative cache, and the sequence of address accesses below, enter the number of misses. CACHE CONFIG 23 23 8 20 9 20...
Below are listed parameters for different direct-mapped cache designs. Cache Data Size: 32 KiB Cache Block...
Below are listed parameters for different direct-mapped cache designs. Cache Data Size: 32 KiB Cache Block Size: 2 words Cache Access Time: 1 cycle Word: 4 bytes. Calculate the total number of bits required for the cache listed above, assuming a 32-bit address. Given that total size, find the total size of the closest direct-mapped cache with 16-word blocks of equal size or greater. Explain why the second cache, despite its larger data size, might provide slower performance than the...
A direct mapped cache has 16 blocks and block size is 64-bits (8 bytes). a. Where...
A direct mapped cache has 16 blocks and block size is 64-bits (8 bytes). a. Where will the memory block 45 reside in cache? (5 b. Where will be the memory address 1667 mapped in cache
Suppose we have a direct-mapped cache that can hold a total of 1024 blocks with 4...
Suppose we have a direct-mapped cache that can hold a total of 1024 blocks with 4 words per block. Compute the block index, block offset, and the tag for the following addresses: (a) 0x11001001 (b) 0x00010014 (c) 0x01000004 (d) 0x01001018 (e) 0x7bdcca10
Computer archieture 1. Assume that the cache size is 512kB, and each cache line is 128...
Computer archieture 1. Assume that the cache size is 512kB, and each cache line is 128 Bytes. If it’s a 4-way associative cache, how many sets are there? If it’s a 2-way associative cache, how many sets are there? Let’s assume the cache is initially empty, and LRU policy is used for cache line replacement. If the following memory blocks are accessed: Mem-block # 7, 1031, 2055, 4103, 1031, 7, 2055, 3079, 1031, 3079 What is the cache hit/miss rate...
A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes...
A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main memory is 300ns. (This time allows us to determine the block is missing and bring it into cache.) Assume a request is always started in parallel to both cache and to main memory(so if it is not found in cache, we do not have to...
pseudo-code, please If a word has a tag O, it means that the word has nothing...
pseudo-code, please If a word has a tag O, it means that the word has nothing to do with the named entity (it is not a part of a named entity such as a location, person name, organization, and etc.) If a word has a tag starting with B, it means that the word is the beginning of a named entity. For instance, the tag B-per means that the associated word is the beginning of a person's name. On the...
11. (12 pts) Consider a system with 32-bit addresses and a 16KB 8-way set-associative cache. Each...
11. (12 pts) Consider a system with 32-bit addresses and a 16KB 8-way set-associative cache. Each cache line contains 64 bytes. (a) How many bits of an address are used for the offset in this cache? (b) How many bits of an address are used for the index in this cache? (c) How many bits of an address are used in the tag for this cache? (d) What is the value of the tag for 0x000d6ae2? (e) What is the...
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT