For a direct mapped cache design with 32 bit address, the following bits of the address...

For a direct mapped cache design with 32 bit address, the following bits of the address are used to access the cache

Tag	Index	Offset
31 - 8	7 - 4	3 - 0

What is the cache block size (in words)?
How many entries does the cache have?
What is the ratio between total bits required for such a cache implementation over the data storage bits?

Starting from power on, the following byte-addressed cache references are recorded.

					Address
0	4	14	132	232	160	1024	30	140	3100	180	2180

How many blocks are replaced?
What is the hit ratio?
List the final state of the cache, with each valid entry represented as a record of <index, tag, data>.

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Expert Solution

venereology answered 10 months ago

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