a) consider a direct mapped cache with 10 blocks of 10 words
each. Suppose main memory...
a) consider a direct mapped cache with 10 blocks of 10 words
each. Suppose main memory is 1000 words. For ewach memory address
below say what cache block it maps to, what is the offset, and what
is the tag.
Suppose a computer using direct mapped cache has 232
bytes of main memory and a cache of 1024 blocks, where each block
contains 32 bytes.
[2] How many blocks of main memory does this computer
have?
[4] Show the format of a memory address as seen by cache; be
sure to include the field names as well as their sizes.
[3] Given the memory address 0x00001328, to which cache block
will this address map? (Give you answer in decimal.)
A...
A direct-mapped cache consists of 8 blocks. Byte-addressable
main memory contains 4K blocks of 8 bytes each. Access time for the
cache is 22ns, and the time required to fill a cache slot from main
memory is 300ns. (This time allows us to determine the block is
missing and bring it into cache.) Assume a request is always
started in parallel to both cache and to main memory(so if it is
not found in cache, we do not have to...
Suppose a computer using direct mapped cache has 224
bytes of byte-addressable main memory, and a cache of 128 blocks,
where each cache block contains 8 bytes. For fully associative
cache, to which block of cache the address 0x189B5A maps?
Group of answer choices
Block 6
Block 75
Not enough information
Block 10
A direct mapped cache has 32 cache
lines.Each cache line consists of 4 words, and each word is four
bytes.The address bus consists of 16 bits.
How many bits are required for the
tag in this direct-mapped cache?
Suppose we have a direct-mapped cache that can hold a total of 1024
blocks with 4 words per block.
Compute the block index, block offset, and the tag for the
following addresses:
(a) 0x11001001
(b) 0x00010014
(c) 0x01000004
(d) 0x01001018
(e) 0x7bdcca10
A computer uses direct-mapped cache with four16-bit words, and
each word has an associ-ated13-bit tag. Consider the following loop
(three instructions) in a program. Before the loop,the values in
registersR0,R1,R2are 0, 054E, and 2 respectively. Consider that
instructions arealready in separate cache memory. (See Table1.)The
loop starts at location LOOP=02EC.LOOPAdd(R1)+,R0;DCRR2;
BR>0LOOPShow the content of cache at the end of each pass of
this loop if direct mapping cache is used.Compute hit rate.
A direct mapped cache has 16 blocks and block size is 64-bits (8
bytes).
a. Where will the memory block 45 reside in cache? (5
b. Where will be the memory address 1667 mapped in cache
Below are listed parameters for different direct-mapped cache
designs.
Cache Data Size: 32 KiB
Cache Block Size: 2 words
Cache Access Time: 1 cycle
Word: 4 bytes.
Calculate the total number of bits required for the cache listed
above, assuming a 32-bit address. Given that total size, find the
total size of the closest direct-mapped cache with 16-word blocks
of equal size or greater. Explain why the second cache, despite its
larger data size, might provide slower performance than the...
For a direct mapped cache design with 32 bit address, the
following bits of the address are used to access the cache
Tag
Index
Offset
31 - 8
7 - 4
3 - 0
What is the cache block size (in words)?
How many entries does the cache have?
What is the ratio between total bits required for such a cache
implementation over the data storage bits?
Starting from power on, the following
byte-addressed cache references are recorded.
Address
0...
Given an 8-word, direct mapped cache, and the sequence of
address accesses below, enter the number of misses.
CACHE CONFIG
24
13
24
10
8
8
Given an 8-word, 2-way set associative cache, and the sequence
of address accesses below, enter the number of misses.
CACHE CONFIG
22
1
9
22
22
22
Given an 8-word, 2-way set associative cache, and the sequence
of address accesses below, enter the number of misses.
CACHE CONFIG
23
23
8
20
9
20...