Question

A new instruction is to be included in our core MIPS instruction subset.

This new true-op instruction is addm rt,disp(rs) which computes the sum of the contents of a memory word plus the contents of the rt register and places the sum back into the rt register.

a) Show the MIPS machine code format required for this new true-op instruction.

b) Are any changes to the multi-cycle datapath required to support this new true-op instruction? If so, describe the required changes.

c) Describe how the FSM (finite state machine) for our MIPS core instruction subset requires to be modified to support this new true-op instruction while continuing to support the other instructions within the subset without changing their behavior. In particular, what new or modified states, control signals and transitions are required?

Answer 1

The MIPS has a 32 bit architecture, with 32 bit instructions, a 32 bit data word, and 32 bit addresses. It has 32 addressable internal registers requiring a 5 bit register address. Register 0 always has the the constant value 0. Addresses are for individual bytes (8 bits) but instructions must have addresses which are a multiple of 4. This is usually stated as “instructions must be word aligned in memory.” There are three basic instruction types with the following formats,

R−type (register)

31 26 25 21 20 16 15 11 10 6 5 0

op

rs

rt

rd

shamt

funct

6bits 5bits   5bits   5bits   5bits 6bits

I−type (immediate)

31 26 25 21 20 16 15 0

op

rs

rt

immediate

6bits 5bits 5bits 16bits

J−type (jump)

31 26 25 0

op

target

6bits 26bits

All op codes are 6 bits. All register addresses are 5 bits

Changes to the datapath for a multi-cycle implementation,

We have found that several additional registers are required in the multi-cycle datapath in order to save information from one cycle to the next. These were the registers IR, MDR, A, B, and ALUOut. The overall hardware complexity may be reduced, however, since the adders required for addressing have been replaced by the ALU. Recall that the primary reason for choosing five cycles was the assumption that the time to obtain a value from memory was the single slowest operation in the datapath. Also, we assumed that the register file operations take a smaller, but comparable, amount of time. If either of these conditions were not true, then quite a different schedule of operations might have been chosen.

Fortunately, after our design of the single cycle processor, we have a good idea of the datapath elements required to implement each individual instruction. We can also seek opportunities to reuse functional blocks in different cycles, potentially reducing the number of hardware blocks (and hence the complexity and cost) of the datapath.

The datapath for the multi-cycle processor is similar to that of the single cycle processor, with

• the addition of the registers noted (IR, MDR, A, B, and ALUOut)

• the elimination of the adders for address calculation

• a MUX must be extended because there are now three separate calculations for the next address (jump, branch, and the normal incrementing of the PC).

• additional control signals controlling the writing of the registers.