Question

It is required to design a synchronous sequential circuit that receives two input bit streams X and Y, and detects identical 4-bit sequences in both X and Y that are non-overlapping. The output Z is also a bit stream that produces a 1 only after detecting two identical 4-bit input sequences. Use an asynchronous reset input to reset the sequential circuit to its initial state.
Example:
X: 001010 110010 0111 1010100 0111
Y: 011010 100010 0111 1000100 0010
Z: 000001 000001 0001 0000001 0000
a) (5 points) Draw a Mealy state diagram of the sequential circuit.
b) (10 points) Implement your design using a minimal number of D-type flip flops and combinational logic. Show the K-maps and write the minimal next state and output equations. Draw the circuit diagram.
c) (10 points) Write a structural Verilog model that models your implemented sequential circuit by modeling the D Flip-Flops and instantiating them and modeling the combinational part using either assign statement or gate primitives.
d) (10 points) Write a test bench that tests your structural Verilog model in (c) using the given input sequence. Start by resetting all flip-flops and then apply the input sequences of X and Y shown above. Verify that your circuit produces the correct output by including the generated waveform from simulation.
e) (10 points) Write a behavioral Verilog description that models your state diagram in part (a).
f) (5 points) Write a test bench that tests your behavioral Verilog model of part (e). Start by resetting all flip-flops and then apply the input sequences of X and Y shown above. Verify that your circuit produces the correct output by including the generated waveform from simulation.
g) Submit a report (Word or PDF document) that should contain:
i. The state diagram of your design (part a).
ii. The K-maps, equations, and circuit diagram of your sequential circuit (part b).
iii. A copy of the Verilog modules and test benches of parts (c) to (f)
iv. The timing diagrams (waveforms) taken directly as snapshots from the simulator for
parts (d) and (f).
Take All the time you need.

Answer 1

Melay FSM: the output of the Melay FSM depends on the present state and present input.