Question

Try designing a 4 bit Multiplexer using two 2-bit multiplexer design given below and verify the design by simulating it.

module Mux2x1(In0,In1,sel,out);
input In0,In1,sel;
output out;
assign out = (sel)?In1:In0;
endmodule

Pls include the verilog design module,testbench, waveform

Answer 1

// verilog code for 2*1 mux

module Mux2x1(In0,In1,sel,out);

input In0,In1,sel;

output out;

assign out = (sel)?In1:In0;

endmodule

// verilog code for 4*1 mux using 2*1 muxes

module Mux4x1 (

// input port declarations

input In0,In1,In2,In3,sel1,sel0,

output out);

  

// internal signal declaration

wire t,u ;

  

// instantiate 2*1 mux modules

  

  

Mux2x1 U0 (.In0(In0),.In1(In1),.sel(sel0),. out (t));

  

Mux2x1 U1 (.In0(In2),.In1(In3),.sel(sel0),. out (u));

  

Mux2x1 U2 (.In0(t),.In1(u),.sel(sel1),. out (out));

  

  

endmodule

  

  

// testbench code for 4*1 mux

module test;

  

reg In0,In1,In2,In3,sel1,sel0;

  

wire out;

  

// instantiate DUT

Mux4x1 A0 (.In0(In0),.In1(In1),.In2(In2),.In3(In3),.sel1(sel1),.sel0(sel0),.out(out));

  

  

// input stimulus

  

initial begin

$dumpfile("dump.vcd");

$dumpvars;

  

In0 =1'b1; In1 = 1'b0;In2 = 1'b1; In3 = 1'b0;

  

sel1 = 1'b0; sel0 = 1'b0; #20;

sel1 = 1'b1; sel0 = 1'b0; #20;

sel1 = 1'b0; sel0 = 1'b1; #20;

sel1 = 1'b1; sel0 = 1'b1; #20 $finish;

  

end

  

endmodule

  

  

  

  

// Simulation waveforms