Question

1. A sequence detector is monitoring a serial input stream looking for either 0101 or 0110. The output is two consecutive cycles of 1’s, with the first of the two being asserted in the same cycle as the last input matching the sequence; in other words, it has to be a Mealy machine.

   1. Draw the state diagram for this sequence detector

   2. Assign states and create the state table, showing next states and output as a function of current state and input. You can call your state, input, and output variables

      anything you want.

   3. Write a Verilog module that implements the behavior

Answer 1

Here i am writing the code.

module detector(xd,y)
input xd;
output y;

module NOT_gate_level(x,xbar);
not (x,xbar);
module AND_4_gate_level(da,qabar,qb,qcbar,x);
AND(da,qabar,qb,qcbar,x);
endmodule
module AND_3_gate_level(c1,qabar,qc,x);
AND(c1,qabar,qc,x);
endmodule
module AND_4_gate_level(c2,qabar,qb,qcbar,xbar);
AND(c2,qabar,qb,qcbar,xbar);
endmodule
module OR_2_gate_level(db,c1,c2);
OR(db,c1,c2);
endmodule
module AND_3_gate_level(a1,qabar,qcbar,xbar);
AND(a1,qabar,qcbar,xbar);
endmodule
module AND_3_gate_level(a2,qabar,qbbar,xbar);
AND(a2,qabar,qbbar,xbar);
endmodule
module AND_4_gate_level(a3,qa,qbbar,qcbar,x);
AND(a3,qa,qbbar,qcbar,x);
endmodule
module OR_3_gate_level(dc,a1,a2,a3);
OR(dc,a1,a2,a3);
endmodule;
module dff_behavioral(da,clk,qa,qabar);
input da,clk;
output reg qa, qabar;
always@(posedge clk)
begin
qa<= da;
qabar = !da;
end
endmodule
module dff_behavioral(db,clk,qb,qbbar);
input db,clk;
output reg qb, qbbar;
always@(posedge clk)
begin
qb<= db;
qbbar = !db;
end
endmodule
module dff_behavioral(dc,clk,qc,qcbar);
input dc,clk;
output reg qc, qcbar;
always@(posedge clk)
begin
qc<= dc;
qcbar = !dc;
end
endmodule
module AND_4_gate_level(output x1,input qabar,qb,qc,x);
AND(x1,qabar,qb,qc,x);
endmodule
module AND_4_gate_level(output x2,input qa,qbbar,qc,x);
AND(x2,qa,qbbar,qc,x);
endmodule
module OR_2_gate_level(output xd,input x1,x2);
OR(xd,x1,x2);
endmodule
begin
y= xd;
end
endmodule

Here I have uploaded the solution.

If you have any doubt or problem, let me know in the comments.