Question

This is the question about Verilog.

the H/W question is "Explain about 'always syntax' in verilog with the simple verilog example."

  

Answer 1

The always block is a type of procedural block in Verilog. The statements inside the always block get executed in a sequential manner.

The syntax of always block is as follows:

always @ (event)

         [statement]

always @ (event) begin

         [multiple statements]

end

The always block gets executed at a specific event. This event is determined by a sensitivity list.

The elements in the always block are set or updated when the sensitivity list gets satisfied.

Sensitivity list

It is the expression which determines the condition when the always block is supposed to be executed. It is defined after @ operator within the parentheses (). It has one or more signals whose value when changed executes the always block.

Use of always block:

It is used for making sequential or combinational elements. A circuit like flip flop is in active state when it is given a clock and a reset.

Example:

// the always block will be executed when value of "a" or "b" change

always @ (a or b) begin

            [statements]

end

If there is no sensitivity list for the always block, then the always block will repeat continuously. The simulation hangs as there will be a no-delay infinite loop.