Question

Choose 1 Microcontroller from each company and write a report on the internal architecture of 3-4 pages

Following are companies:

◼️Intel ◼️Analog Devices ◼️TI ◼️Atmel ◼️AMD

Answer 1

Intel :-

8051 microcontroller is designed by Intel in 1981. It is an 8-bit microcontroller. It is built with 40 pins DIP (dual inline package), 4kb of ROM storage and 128 bytes of RAM storage, 2 16-bit timers. It consists of are four parallel 8-bit ports, which are programmable as well as addressable as per the requirement. An on-chip crystal oscillator is integrated in the microcontroller having crystal frequency of 12 MHz.

Let us now discuss the architecture of 8051 Microcontroller.

In the following diagram, the system bus connects all the support devices to the CPU. The system bus consists of an 8-bit data bus, a 16-bit address bus and bus control signals. All other devices like program memory, ports, data memory, serial interface, interrupt control, timers, and the CPU are all interfaced together through the system bus.

The pin diagram of 8051 microcontroller looks as follows −

• Pins 1 to 8 − These pins are known as Port 1. This port doesn’t serve any other functions. It is internally pulled up, bi-directional I/O port.

• Pin 9 − It is a RESET pin, which is used to reset the microcontroller to its initial values.

• Pins 10 to 17 − These pins are known as Port 3. This port serves some functions like interrupts, timer input, control signals, serial communication signals RxD and TxD, etc.

• Pins 18 & 19 − These pins are used for interfacing an external crystal to get the system clock.

• Pin 20 − This pin provides the power supply to the circuit.

• Pins 21 to 28 − These pins are known as Port 2. It serves as I/O port. Higher order address bus signals are also multiplexed using this port.

• Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to read a signal from the external program memory.

• Pin 30 − This is EA pin which stands for External Access input. It is used to enable/disable the external memory interfacing.

• Pin 31 − This is ALE pin which stands for Address Latch Enable. It is used to demultiplex the address-data signal of port.

• Pins 32 to 39 − These pins are known as Port 0. It serves as I/O port. Lower order address and data bus signals are multiplexed using this port.

• Pin 40 − This pin is used to provide power supply to the circuit.

Analog Devices :-

Blackfin Processor Architecture

Blackfin Processors are a new breed of 16-32-bit embedded microprocessor designed specifically to meet the computational demands and power constraints of today's embedded audio, video and communications applications. Based on the Micro Signal Architecture (MSA) jointly developed with Intel Corporation, Blackfin Processors combine a 32-bit RISC-like instruction set and dual 16-bit multiply accumulate (MAC) signal processing functionality with the ease-of-use attributes found in general-purpose microcontrollers. This combination of processing attributes enables Blackfin Processors to perform equally well in both signal processing and control processing applications-in many cases deleting the requirement for separate heterogeneous processors. This capability greatly simplifies both the hardware and software design implementation tasks.

The Blackfin Processor family also offers industry leading power consumption performance down to 0.8V. This combination of high performance and low power is essential in meeting the needs of today's and future signal processing applications including broadband wireless, audio/video capable Internet appliances, and mobile communications.

All Blackfin Processors offer fundamental benefits to the system designer which include:

• High-performance signal processing and efficient control processing capability enabling a variety of new markets and applications.
• Dynamic Power Management (DPM) enabling the system designer to specifically tailor the device power consumption profile to the end system requirements.
• Easy to use mixed 16-/32-bit Instruction Set Architecture and development tool suite ensuring that product development time is minimized.

High Performance Processor Core

The Blackfin Processor architecture is based upon a 10-stage RISC MCU/DSP pipeline with a mixed 16-/32-bit Instruction Set Architecture designed for optimal code density. Blackfin processors architecture is also fully SIMD compliant and includes instructions for accelerated video and image processing. The architecture is well suited for full signal processing / analytical capabilities while also offering efficient RISC MCU control tasking capabilities - on either a single or dual core device. With the optimal code density and the possibility of little to no code optimization, quicker time to market can be achieved without running into performance headroom barriers seen on other traditional processor.

High Bandwidth DMA Capability

All Blackfin Processors have multiple, independent DMA controllers that support automated data transfers with minimal overhead from the processor core. DMA transfers can occur between the internal memories and any of the many DMA-capable peripherals. Transfers can also occur between the peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller.

Video Instructions

In addition to native support for 8-bit data, the word size common to many pixel processing algorithms, the Blackfin Processor architecture includes instructions specifically defined to enhance performance in video processing applications. For example, Discrete Cosine Transform (DCT) is supported with an IEEE 1180 rounding operation, while the "SUM ABSOLUTE DIFFERENCE" instruction supports motion estimation algorithms used in video compression algorithms such as MPEG2, MPEG4, and JPEG.

Implementing video compression algorithms in software allows OEMs to adapt to evolving standards and new functional requirements without hardware changes. The enhanced instructions allow Blackfin Processors to be considered in applications previously addressed primarily by ASICs, VLIW media processors or hardwired chipsets. Ultimately, Blackfin Processors will help lower overall system cost while improving the time to market for the end application.

Efficient Control Processing

The Blackfin Processor architecture also offers a variety of benefits most often seen in RISC control processors. These features include a powerful and flexible hierarchical memory architecture, superior code density, and a variety of microcontroller-style peripherals including items such as 10/100 Ethernet MAC, UARTS, SPI, CAN controller, Timers with PWM support, Watchdog Timer, Real-Time Clock, and a glueless synchronous and asynchronous memory controller. All of these features provide the system designer with a great deal of design flexibility while minimizing end system costs.

Hierarchical Memory

The Blackfin Processor memory architecture provides for both Level 1 (L1) and Level 2 (L2) memory blocks in device implementations. The L1 memory is connected directly to the processor core, runs at full system clock speed, and offers maximum system performance for time critical algorithm segments. The L2 memory is a larger, bulk memory storage block that offers slightly reduced performance, but still faster than off-chip memory.

The L1 memory structure has been implemented to provide the performance needed for signal processing while offering the programming ease found in general purpose microcontrollers. This is accomplished by allowing the L1 memory to be configured as SRAM, cache, or a combination of both. By supporting both SRAM and cache programming models, system designers can allocate critical real time signal processing data sets that require high bandwidth and low latency into SRAM, while storing more 'soft' real time control / OS tasks in the cache memory.

The Memory Management Unit provides for a memory protection format that, when coupled with the core's User and Supervisor modes, can support a full Real Time Operating System. The RTOS runs in Supervisor mode and partitions blocks of memory and other system resources for the actual application software to run in User mode. Thus, the MMU offers an isolated and secure environment for robust systems and applications.

Superior Code Density

The Blackfin Processor architecture supports multi-length instruction encoding. Very frequently used control-type instructions are encoded as compact 16-bit words, with more mathematically intensive signal processing instructions encoded as 32-bit values. The processor will intermix and link 16-bit control instructions with 32-bit signal processing instructions into 64-bit groups to maximize memory packing. When caching and fetching instructions, the core automatically fully packs the length of the bus because it does not have alignment constraints. When combined, these two features enable Blackfin Processors to deliver code density benchmarks comparable to industry-leading RISC processors.

Dynamic Power Management

All Blackfin Processors employ multiple power saving techniques. Blackfin Processors are based on a gated clock core design that selectively powers down functional units on an instruction-by-instruction basis. Blackfin Processors also support multiple power-down modes for periods where little or no CPU activity is required. Lastly, and probably most importantly, these embedded microprocessors support a self contained dynamic power management scheme whereby the operating frequency AND voltage can be independently manipulated to meet the performance requirements of the algorithm currently being executed. These transitions may occur continually under the control of an RTOS or user firmware. Most Blackfin processors offer on-chip core voltage regulation circuitry as well as operation to as low as 0.8V and are particularly well suited for portable applications requiring extended battery life.

Easy to Use

A single Blackfin Processor can be utilized in many applications previously requiring both a high performance signal processor and a separate efficient control processor. This benefit greatly reduces development time and costs, ultimately enabling end products to get to market sooner. Additionally, a single set of development tools can be used, which decreases the system designer's initial expenses and learning curve.

TI :-

The MSP430 is a family of 16-bit RISC microcontrollers produced by Texas Instruments. The MSP430 microcontroller was developed at Texas Instruments in 1993. At the beginning Texas Instruments only offered the MSP430 in Europe. Since 1997 the MSP430 microcontroller family is offered world wide. The most important feature of the MSP430 is its low power consumption. However, the flexibility of its peripheral modules and the easy way to use it is the reason why this microcontroller is also used as a general purpose microcontroller.

Architecture

The MSP430 microcontroller is based on a von-Neumann architecture. The MSP430 von-Neumann architecture has one address space shared with special function registers (SFRs), peripheral control registers, RAM, and Flash/ROM memory. At the moment there are two compatible CPUs existing within the MSP430 microcontroller family. The MSP430 CPU uses 16-bit CPU register and 16-bit Program Counter. This basically means that with such a CPU an address range of 64kBytes could be addressed. Due to the von-Neumann architecture the address range covers peripheral control registers (address 0x0000 to 0x01FF), RAM (starting at address 0x0200), and for example Flash memory (e.g. for an MSP430F169 the Flash memory starts at address 0x1000). So the MSP430 derivatives with the MSP430 CPU usually have a maximum Flash memory of 60KByte. The other CPU is the MSP430 CPUx (or MSP430X). This is an extended CPU. The CPU registers are 20-bit registers. Also the Program Counter is a 20-bit register, which allows to address memory above the 64KByte limit that was seen before. Usually all MSP430s with a Flash memory above 60kByte Flash have the CPUx. Because the CPUx is based on MSP430 CPU the software that was written on a MSP430 CPU device is also running on MSP430 CPUx chips.

ADC12

The ADC12 module is a 12-bit SAR A/D converter. There is an input multiplexer that allows to select different internal or external analog input signals. Internal analog signals are a temperature sensor signal, half of the supply voltage (that could be used for a battery check), or the external positive and negative reference voltages. Sample rate can be adjusted by software and it can be up to 200ksps. Sample time can be defined by an integrated Sample Timer, by software using a control bit, or by output signals of Timer modules that are also available on MSP430. There are external pins or an integrated reference that can be selected as a reference voltage for the A/D converter core. The internal reference can be switched in 2.5V or 1.5V mode. Separate activation of the reference and ADC core allows reduction of current consumption.

ADC10

The ADC10 module looks similar like the ADC12. The ADC10 module is a SAR A/D converter. There is an integrated reference (1.5V, 2.5V, or external reference can be chosen). A sample timer allows the adjustment of the sample time. Beside the analog inputs there is also the possibility to choose a Vcc half voltage or a temperature sensor signal (integrated temperature sensor) as the analog input signal. Vcc half voltage can be used to measure the battery voltage that is usually directly applied to the Vcc pins of the MSP430. Main difference compared with ADC12 is the realization of the autoscan function. The ADC10 module uses a Data Transfer Controller (DTC) to move the conversion results to a definable source address - this means conversion results can be stored in RAM, Flash, or peripheral control registers. The sample rate of the ADC10 module is also in the range of up to 200ksps.

DAC12

The DAC12 module is a 12-bit monotonic voltage output D/A converter. Usually there are existing several DAC channels (up to 2). It can be configured in 8-bit or 12-bit output resolution. It was designed for optimized power consumption. So features can be found like programmable settling time versus power consumption. It is possible to select either the ADC12 reference or an external reference voltage as the reference voltage for the DAC12. Self-calibration option for offset correction and synchronized update capability for multiple DAC12 channels are available.

Analog Comparator

The Comparator_A or Comparator_A+ modules are analog comparators. It is possible to choose chip internal thresholds (0.25*Vcc, 0.5*Vcc, or a diode voltage as reference or temperature sensor). The internal connection of the comparator output to a capture input of a timer module allows charge/discharge time measurements, which makes it simple to realize a resistive measurement (e.g. using NTC to measure temperature). Especially ratiometric measurements allow to do conversion with a resolution of around 11-bits and higher.

Digital Peripheral Modules

Development Tools

A simple and cheap Starter Kit (eZ430-F2013)

This is a simple and cheap tool that is perfect to start with MSP430. It supports the MSP430F20x1, MSP430F20x2, and MSP430F20x3 devices. The eZ430-F2013 tool looks like an USB Stick. The USB stick consist of two parts. First the USB emulator and a removable target board. The eZ430-F2013 is delivered with one target board that uses an MSP430F2013. If someone wants to use an MSP430F2012 instead of the 'F2013 there are also a kit with 3 eZ430 target boards using MSP430F2012 available (eZ430-T2012).

A cheap wireless Starter Kit (eZ430-RF2500)

This one uses the same USB emulator than the eZ430-F2013. However, there are different target boards that uses beside an MSP430F2274 and CC2500. The kit is delivered with 2 RF boards, one battery holder, the USB emulator, and a CD ROM.

The LaunchPad (MSP-EXP430G2)

A very low-cost ($4.30) experimenter's board created with beginners and hobbyists in mind. Comes as a complete, assembled product (except for the header pins) with two MSP430 controllers, an external crystal, a USB cable, and freely downloadable development environments

Atmel :-

Atmega32 belongs to Atmel family and its architecture as follows:-

PIN count: Atmega32 has got 40 pins. Two for Power (pin no.10: +5v, pin no. 11: ground), two for oscillator (pin 12, 13), one for reset (pin 9), three for providing necessary power and reference voltage to its internal ADC, and 32 (4×8) I/O pins.

About I/O pins: ATmega32 is capable of handling analogue inputs. Port A can be used as either DIGITAL I/O Lines or each individual pin can be used as a single input channel to the internal ADC of ATmega32, plus a pair of pins AREF, AVCC & GND (refer to ATmega32 datasheet) together can make an ADC channel.

No pins can perform and serve for two purposes (for an example: Port A pins cannot work as a Digital I/O pin while the Internal ADC is activated) at the same time. It’s the programmers responsibility to resolve the conflict in the circuitry and the program. Programmers are advised to have a look to the priority tables and the internal configuration from the datasheet.

Digital I/O pins: ATmega32 has 32 pins (4portsx8pins) configurable as Digital I/O pins.

Timers: 3 Inbuilt timer/counters, two 8 bit (timer0, timer2) and one 16 bit (timer1).

ADC: It has one successive approximation type ADC in which total 8 single channels are selectable. They can also be used as 7 (for TQFP packages) or 2 (for DIP packages) differential channels. Reference is selectable, either an external reference can be used or the internal 2.56V reference can be brought into action. There external reference can be connected to the AREF pin.

Communication Options: ATmega32 has three data transfer modules embedded in it. They are

• Two Wire Interface
• USART
• Serial Peripheral Interface

Atmega32 pin diagram

Analog comparator: On-chip analog comparator is available. An interrupt is assigned for different comparison result obtained from the inputs.

External Interrupt: 3External interrupt is accepted. Interrupt sense is configurable.

Memory: It has 32Kbytes of In-System Self-programmable Flash program memory, 1024 Bytes EEPROM, 2Kbytes Internal SRAM. Write/Erase Cycles: 10,000 Flash / 100,000 EEPROM.

Clock: It can run at a frequency from 1 to 16 MHz. Frequency can be obtained from external Quartz Crystal, Ceramic crystal or an R-C network. Internal calibrated RC oscillator can also be used.

More Features: Up to 16 MIPS throughput at 16MHz. Most of the instruction executes in a single cycle. Two cycle on-chip multiplication. 32 × 8 General Purpose Working Registers

Debug: JTAG boundary scan facilitates on chip debug.

Programming: Atmega32 can be programmed either by In-System Programming via Serial peripheral interface or by Parallel programming. Programming via JTAG interface is also possible. Programmer must ensure that SPI programming and JTAG are not be disabled using fuse bits; if the programming is supposed to be done using SPI or JTAG.

Atmega32 block diagram