PLC systems

We have three different motors to work at an irrigation facility. We can only use a START button to run the system and a STOP button to stop the system.

System Conditions to Work:
*When we pressed START button first motor has to work non-stop, after 25 seconds second motor has to work non-stop and first motor has to keep working at this time. 40 seconds after second motor starts we also need third motor to START in this time first and second motors has to keep working by the way. 60 seconds after third motor starts all motors have to STOP together.

a) Write all the buttons, motors, relays and other components and their names on PLC program as a list.
b) Draw input/output connections as a schema and write names of included components.
c) Draw LADDER diagram of this program.

Could you please write this program on PLC system without using TIMER, paper or a screenshot is pretty enough but I would love to see screenshot if its possible. Thanks in advance. Stay safe!

Lab report on **KVL & KCL**
Should have Profile or definition and simple steps to analyze the electrical circuit through the KVL & KCL and example.
#Please write clearly or work on word.

Demonstrate with simple examples on under-sampling and over-sampling effects. Give exact parameters and data in your demonstrating example. Explain in terms of sampling theorem, Nyquist rate, low pass filter effect.

Three equal impedances, (8+j6) ohms are connected in wye across a three-phase, three-wire supply. The symmetrical components of the phase A line voltages are:

Va0 = 0

Va1 = 220 + j 28.9 V

Va2 = -40 - j 28.9

If there is no connection between the load neutral and the supply neutral, Calculate the symmetrical currents of line a,b, and c.

a three-phase bipolar motor of 10.72 [HP] has an efficiency of 80% when working at full load at 2700 (rpm), if it is connected to a network of 440 (V) at 50 [Hz] calculate

a.) The synchronous motor speed in (rpm)
b.) Engine displacement.

c.) rotor frequency at full load.

d.) If the kilowatt hour costs $ 185.39. The money saved in energy consumption if the engine works continuously for three years and is replaced by an engine with 97% efficiency?

covert -19.875 to the following:

i) Two's complement

ii) Octal

iii) Hexadecimal

iv) Gray code

What are the factors that influence the trauma caused by an electric arc? How do they impact the trauma?

Hello, i am currently working on an attendance system using MATLAB by the comparison of 2 images of the same class, does anyone have any ideas or methods to use

Consider a finite state machine with a control input called mode. When mode = 0, the machine operates as a mod-3 down counter, where the outputs are the count values. When mode = 1, the machine's output progresses through the last 4 digits of your WCU ID (1133) number (1 digit per clock cycle). Complete each of the steps which follow.

(a) Draw the state diagram for this machine.
(b) Write RTL Verilog code which implements this design. Submit your printed source code by the due date and time.
(c) Create a test bench to exercise the design through all of its states and functions. Submit your test bench source code and a simulation waveform. The simulation waveform must show the digits of your WCU ID and no one else's.

1. How many complex numbers z are there such that z³ = 1?

2. Translate x(t) = -cos(πt + π/3) into standard form A⋅sin(2πft + φ) (There are multiple correct answers)

3. If f_s = 100 Hz, what are three aliasing frequencies for f = 80 Hz?

4. A signal x is delayed by one sample and scaled by −1/2, producing a new signal y[n] = −1 2 x[n − 1]. (a) How does Y[m] relate to X[m]? (b) What about |Y[m]| and |X[m]|?

5. If a signal x’s DFT has entirely real coefficients X[m] (has no imaginary component), what can you deduce about x? Consider the phase for each analysis frequency.

6. Let x[n] be a signal with N = 5000 samples. (a) If you compute an STFT with a frame length of K = 1000 and hop length h = 250, what will be the shape of the resulting spectrogram? (b) How would it change if you set K = 2000? (c) What if you set h = 100?

gow does scan expansion mesh and scan expansion meshless work in a oscilliscope?
in other words what happens inside an oscilliscope when i turn the time/div knob?

PN Junctions and breakdown

1. Draw and interpret energy band diagram for pn junction in equilibrium, forward, and reverse bias

2. Describe what physically happens (And why) when you put n-Si in contact with p-Si (e.g., junction formation)

3. Calculate Vo, W, Wn, Wp

4. Describe how/why current flows in forward and reverse bias.

5. Utilize law of junction to calculate the minority carrier concentration just outside the depletion layer

6. Quantify the forward and reverse bias current in a p-n junction given appropriate information

7. Describe the meaning of the diode ideality factor for values of 1 and 2 and in between

8. Describe what constitutes “short diode” conditions

9. Calculate the depletion layer capacitance given sufficient information

10. Identify the two mechanisms that allow for reverse bias breakdown of a diode.

11. Describe what occurs during Zener tunneling and avalanche and the conditions that this will occur

This concept of  (A/D conversion and sampling rates) could be relevant to envisioned future career field.

Could you write a paragraph commenting please?

module traffic(clk, reset, P1, P2, P3, P4, PL);
input clk;
input reset;
output[4:0] P1;
output[4:0] P2;
output[4:0] P3; // four roads
output [4:0] P4;
output[3:0] PL; //Pl is pedestrian

reg [4:0] P1;
reg [4:0] P2;
reg [4:0] P3;
reg [4:0] P4;
reg [3:0] PL;
reg [4:0] sig;

always @(posedge clk or negedge reset)
begin
   if(reset == 1'b0)begin
       P1 <= 5'b00100;
       P2 <= 5'b00100;
       P3 <= 5'b00100;
       P4 <= 5'b00100;
       PL <= 4'b1111;
       sig <= 5'b00000;
   end
   else begin
       sig <= sig + 1;
      
       case(sig[4:0])
       5'b00000:begin
       P1 <= 5'b10011; //path 1 is greeen
       P2 <= 5'b00100; //all other paths are red
       P3 <= 5'b10011;
       P4 <= 5'b10011;
       PL <= 4'b1111;
       end
      
       5'b00100:begin
       P1 <= 5'b01000; //path 1 is yellow
       P2 <= 5'b00100; // all other paths are red
       P3 <= 5'b00100;
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b01000:begin
       P1 <= 5'b00100; //path 1 is red
       P2 <= 5'b10011; //path 2 is green
       P3 <= 5'b00100; // all other paths are red
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b01100:begin
       P1 <= 5'b00100;
       P2 <= 5'b01000; //path 2 is yellow
       P3 <= 5'b00100; // all other paths are red
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b10000:begin
       P1 <= 5'b00100;
       P2 <= 5'b00100; //path 3 is green
       P3 <= 5'b10011; // all other paths are red
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b10100:begin
       P1 <= 5'b00100;
       P2 <= 5'b00100; //path 3 is yellow
       P3 <= 5'b01000; // all other paths are red
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b11000:begin
       P1 <= 5'b00100;
       P2 <= 5'b00100; //all other paths are red
       P3 <= 5'b00100; // path 4 is yello
       P4 <= 5'b10011;
       PL <= 4'b1111;
       end

       5'b11100:begin
       P1 <= 5'b00100; //all other paths are red
       P2 <= 5'b00100;
       P3 <= 5'b00100;
       P4 <= 5'b00100;
       PL <= 4'b0000; //pedestrian green
       end

       5'b11111:sig<= 6'b00000;

       default:begin     
      
       end
   endcase

   end
end

endmodule

can anyone write a testbench for this code in Verilog.