Please write and solve one question about ideal transformer (parametric). Also, please write and solve one more question about a real transformer (numerical). You can get help from the Electric Machinery. A.E. Fitzgerald book. (Add approximations if any) I'm waiting for two questions with answers to learn transformers in detail.

I am in this electrical engineering project course in which an assignment is asking me this and I cannot make heads or tails of what it means by this...

Discuss the tradeoffs involved between using patents and trade secrets to protect intellectual property.

Please be as descriptive as possible,

THANKS

considering the measurement of liquid level, explain with the aid of a diagram the principle by which the ultrasonic liquid level gauge operates

A resonant loop antenna of closely spaced 8 turns is operating at 100 MHz. The radius of the loop
is λ/20, and the loop is connected to a 75-Ω transmission line. The radius of the wire is λ/300, its
conductivity σ = 5.7 × 107 S/m, and the spacing between the turns is 3λ/250. Find the radiation
efficiency of the antenna, while taking into account the proximity effects of the turns.

1. A rocket is launched straight into the air with initial velocity 200 ft/s. Assume the launch is instantaneous. How high will it go, and how long will that take (use time increments of 0.01 seconds)? G= - 32.2 ft/s² , H₀=0 (the ground)

V(t)=V₀ + g t

H(t)= H₀ + V₀ t + ½ g t²

The rocket deploys a parachute after 9 seconds and descends at a constant rate of 20 ft/sec. How long does it take to reach the ground?write that by matlab program only

Plot the velocity and the height as functions of time on a single plot. Fully format the figure.

By matlab program please

In a 500/250 V d.c. 3-wire system, there is a current of 2000 A on the +ve side, 1600A on the negative side and a load of 300 kW across the outers. The loss in each balancer set is 8 kW. Calculate the current in each armature of the balancer set and total load on the main generator.

For each of the statements given below, indicated “True” or “False”.

(a) The address issued by the processor is the address of a location in the cache.

(b) The main memory is larger than the cache.

(c) All data and instructions stored in secondary memory are also stored in main memory.

(d) The cache has a shorter access time than main memory.

(e) Main memory is typically constructed using DRAM technology.

explain why

1. A collector-modulated power has a supply voltage of 48V and an average collector current of 600 mA. Determine: a) the input power to the transmitter? b) the modulating signal power needed to produce 100% modulation?

2) …. receivers convert all incoming signals to a lower, fixed frequency.

3) List all the frequencies that emerge from a mixer that is fed with an incoming frequency of 107.1 MHz and another frequency of 96.4 MHz

4. What is the Image Frequency that results from the signal frequency and local oscillator frequency?

F_S = 90 MHz              F_LO = 100 MHz           F_IMAGE=?

5) List all the frequencies that emerge from a mixer that is fed with an incoming frequency of 107.1 MHz and another frequency of 96.4 MHz. Which frequency is normally filtered out in a modern receiver?

a) AM transmitters more commonly use low-level modulation, while FM transmitters more commonly use high-level modulation. True or False

b) Explain the basic elements of a Single Side Band (SSB). What element distinguishes it from a DSB transmitter?

c) As regulated by FCC law, what component is used to generate the carrier frequency of broadcast transmitters?

d) A …. uses a ROM look-up table to generate sinewaves or other signal types for carrier signal generation.

e) Explain the difference between a Class C amplifier and Class A-B amplifier.

6. What would you use to interface a balanced output to an unbalanced input?

Consider the "Successive Approximation" based ADC with a 5-bit converter and a voltage range of 0 to 5.0 volts. Show how it would approximate an incoming analog voltage value of 1.723 volts using a drawing of volts vs. discrete time steps associated with sampling. Show each approximation step (upper and lower bound voltage limits), show final A/D Output in Hex and show Vmin-max and the actual error in this approximation as a voltage and as a percentage of the actual voltage.

Project Summary

A company asks you to design a controller for a basketball machine that will indicate that a
player has won a game if they get a total of 3 points. There are two sensors in this machine. One
in the backboard and on the inside of the orange rim. If a player shoots a shot and the ball hits the
backboard and the ball goes through the rim, then the play will gain 1 point. If the player shoots
the ball and it doesn't hit the backboard and the ball just goes through the rim, then the play will
gain 2 points. If the player hits the backboard and the ball does not go through the rim, then the
player will lose 1 point. The total score can only go down to zero and cannot become negative. If
the ball does not go through the rim or hit backboard, then it will count as a no shot and nothing
will happen. Once the player scores three points, the game ends, and a light will indicate that the
player has won.

Deliverables
• You need to design TWO finite-state synchronous machines so that the company can
pick one that appears more suitable. However, you should pick your favorite and come up
with convincing arguments why you favor one design over the other. You, for example,
can build a Moore design and a Mealy design and compare them. You should use D flip
flops for your designs. Mixing different types of flip flops with different trigger edge
sensitivity is possible but not recommended. Note that two designs which differ by only
the type of flip flop (e.g., J-K vs. D) or number of states (i.e., changing the type of FF or
inserting more unnecessary states) is not considered conceptually different.

1. A testbench is provided in the following directory (~lab_work/verification/task3) without the Device Under Test (DUT).(see testbench below)

`timescale 1ns/10ps

module tb_detector ;

reg clk, rst, datain;
wire det;

detector DUT ( .clk(clk), .rst(rst), .datain(datain), .det(det) );


initial
begin
#0 clk = 0;
datain = 0;
forever #5 clk = ~clk;
end

initial
begin
#0 rst = 0;
@ (negedge clk);
@ (negedge clk);
rst = 1;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 1;

@(posedge clk)
#2 if (det == 1)
$display ("det = %b, correct output", det);
else
$display ("det = %b, incorrect output", det);

@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 0;

@(posedge clk)
#2 if (det == 0)
$display ("det = %b, correct output", det);
else
$display ("det = %b, incorrect output", det);

@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 1;

@(posedge clk)
#2 if (det == 1)
$display ("det = %b, correct output", det);
else
$display ("det = %b, incorrect output", det);

@ (negedge clk);
datain = 1;

#100 $finish;
end



endmodule

2. Write a verilog code for the DUT that will do the following:

i) receive clk, rst dan datain signals from the provided testbench

ii) reset the output signal to LOW synchronously with the positive (rising) edge of clk when rst is set LOW

iii) produce an output signal similar to datain when rst is HIGH and the output transition occurs at the negative (falling) edge of clk.

3. Verify the design using the testbench.

1) Identify what are the factors and impacts that will influence the electricity demand growth rate.