sir I want to make discrete time Fourier series on GUI MATLAB can any one tell me step by step procedure or coding for Discrete time Fourier series on GUI? pleaseeeee

Create a state meachine that encrypts an incoming digital bitstream using a D-flip-flop and a Mealy Meachine. The device have to meet these requirments:

A. The output of the encryption device matches the input bitstream until a certain set of bits is detected (such as 110). After this detection, the output is the complemented version of the input.

B. When a second bitstream 010 is detected, the output reverts to simply matching the input stream again. Please make both bitstreams that cause the switching action to be at least 3 bits in length.

Please include the following for the above questions:

1. A state graph for the machine.

2. The state tables, truth tables, and K-maps that you used to design the machine.

3. Give the example bitstream output demonstrating the machine in operation. Example bitstream: 0111010001110101

Approximately how many ft (m) of cable are required to connect the oven in the residence?

Can someone create a Test bench for this 4 Bit USR code so that it can shift left, shift right and Load. This is in VHDL. Please type out the code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Uni_reg is
port( LR,SP,clk,clear,shL,shR: in std_logic; -- shL = shift left shR= shift right
Da,Db,Dc : in std_logic; --inputs for load
Qa,Qb,Qc : out std_logic); --out puts from the flipflops
end Uni_reg;

architecture Structural of Uni_reg is

signal lr1,lr2,sp1,sp2,R1,R2,R3 : std_logic;
signal L1,L2,L3,LOAD1,LOAD2,LOAD3:std_logic;
signal c1,c2,c3 : std_logic;
signal Qas,Qbs,Qcs : std_logic;

component andgate
port(a,b,c : in std_logic; z : out std_logic);
end component;

component orgate
port(a,b,c : in std_logic; z : out std_logic);
end component;

component notgate
port(a: in std_logic; z : out std_logic);
end component;

component Dflipflop
port(D,clk: in std_logic; Q: out std_logic);
end component;

begin

NOTGATE1: notgate port map (LR,lr1);--1st notgate for LEFT/RIGHT
NOTGATE2: notgate port map (lr1,lr2);--2nd notgate for LEFT/RIGHT
NOTGATE3: notgate port map (SP,sp1);--1st notgate for SERIAL/PARRALLEL
NOTGATE4: notgate port map (sp1,sp2);--2nd notgate for SERIAL/PARRALLEL

ANDGATE1: andgate port map (shR,sp2,lr2,R1); --for right shift of 1st bit
ANDGATE2: andgate port map (sp2,lr1,Qbs,L1); --for left shift of 1st bit
ANDGATE3: andgate port map (lr2,sp1,Da,LOAD1);--for load of 1st bit
ANDGATE4: andgate port map (Qas,sp2,lr2,R2); --for right shift of 2nd bit
ANDGATE5: andgate port map (sp2,lr1,Qcs,L2); --for left shift of 2nd bit
ANDGATE6: andgate port map (lr2,sp1,Db,LOAD2);--for load of 2nd bit
ANDGATE7: andgate port map (Qbs,sp2,lr2,R3); --for right 3rd bit
ANDGATE8: andgate port map (sp2,lr1,shL,L3); --for left 3rd bit
ANDGATE9: andgate port map (lr2,sp1,Dc,LOad3);--for loading 3rd bit

ORGATE1: orgate port map (R1,L1,LOAD1,c1);--for the 1st flipflop
ORGATE2: orgate port map (R2,L2,LOAD2,c2);--for the 2nd flipflop
ORGATE3: orgate port map (R3,L3,LOAD3,c3);--for the 3rd flipflop

FLIPFLOP1: Dflipflop port map (c1,clk,Qas);
FLIPFLOP2: Dflipflop port map (c2,clk,Qbs);
FLIPFLOP3: Dflipflop port map (c3,clk,Qcs);

process(clk,clear)
begin
if clear ='1' then
c1<='0';
elsif (clk'event and clk = '1') then
c1<=c1;
Qa <= c1;
end if;
end process;

process(clk,clear)
begin
if clear ='1' then
Qbs<='0';
elsif (clk'event and clk = '1') then
Qbs<= Qbs;
Qb <= Qbs;
end if;
end process;

process(clk,clear)
begin
if clear ='1' then
Qcs<='0';
elsif (clk'event and clk = '1') then
Qcs<=Qcs;
Qc <= Qcs;
end if;
end process;

end Structural;

For Bi-convex lens, Bi-concave lens Concave Mirror and Concave mirror :

1 ) By looking at the lens and mirrors in person, comment on the orientation and location of the images you see?

2 )How could these types of lens be used for lighting purposes?

The heater element of a kettle has a constant resistance of 105ohm and apllied voltage of 240V
Calculate the time taken to raise the temperature of on litre of water from 15degrees celsius to 90 degrees celsius assuming that only 80% of the power input to the kettle is usefully employed
If the water equivalent of the kettle is 150g, find out how long it will take tobraise a second litre of water through the same temperature range immediately after the first time.

can someone explain to me a the design of macro in verilog(high level view)?

Explain the following code. What language? What does it do? What is the result?

                <!DOCTYPE teo[

                                <ELEMENT teo((stations| databases)+)>

                                <ELEMENT stations(stationName stationLocation sensors*)>

<ELEMENT databases(databaseName databaseType )>

<ELEMENT stationName(#PCDATA)>

<ELEMENT stationLocation(#PCDATA)>

<ELEMENT sensors (sensorName phenomenon)+>

<ELEMENT sensorName(#PCDATA)>

<ELEMENT phenomenon(#PCDATA)>

<ELEMENT databaseName(#PCDATA)>

<ELEMENT databaseType(#PCDATA)>

<!ATTLIST stations boundingBox CDATA #required>

]>

Design a Moore state machine that has an input w and an output z that should output a ‘1’ when the previous 4 values of w were 1001 or 1111. Overlapping patterns are allowed. Show the state diagram and state table. Use a simple binary counting order for the state assignment. Derive all of the next-state and output equations. You do not need to draw the resulting circuit, instead write a Verilog module for it.

Explain the following code. What language? What does it do? What is the result?

SELECT date_trunc('month',date),avg(value)

FROM rain

GROUP BY date_trunc ('month',date)

ORDER BY date_trunc('month',date);

Explain the following code. What language? What does it do? What is the result?

SELECT date_trunc('month',date),avg(value)

FROM rain

GROUP BY date_trunc ('month',date)

ORDER BY date_trunc('month',date);

Design a bandpass active filter to pass frequencies between 700 Hz and 2100 Hz, and with K= 63.

Please include the transfer function, blot plot, multisim, and the matlab code.

In ATmega328P What register are available? Address? Data? Special? Other?

Hello, Do you mind to list the registers as classified under either address, data , special and others

Q13. A buck converter is constructed with a MOSFET which has an on-state resistance of 75m?, and a diode with a forward voltage drop of 1.3V. The MOSFET exhibits switching rise and fall times of 50ns. The converter operates from an input voltage of 400V and. The converter supplies 1.2kW at an output voltage of 300V and switches at 150kHz. The MOSFET and the diode are mounted onto separate heatsinks. The ambient temperature in which the power converter operates is 45°C.

Other thermal data are:

MOSFET Junction to case thermal resistance, R?jc 0.5°C/W, Case to heatsink thermal resistance, R?chs 1.2°C/W

Diode Junction to case thermal resistance, R?jc 0.8°C/W ,Case to heatsink thermal resistance, R?chs 1.5°C/W

(a) Calculate the power dissipation in the MOSFET.

(b) Calculate the power dissipation in the diode.

(c) Calculate the thermal resistance of each heatsink if the temperature of the devices’ junctions is to be restricted to 110°C.  

6.2 Name the three key components of a phase locked loop and write a brief explanation of how each component works.