Please elaborate on how to obtain circular polarization using rectangular microstrip antenna and explain why circular polarization can be achieved by doing so.
In: Electrical Engineering
define, in any form, what is meant by a kW-hr of energy. Write up your analysis in a professional technical memorandum
In: Electrical Engineering
Hey i am a Electrical Engineering student
So as we all know due to this pandemic situation universities are
closed.
So we were not able to work on our lab Hardware part so we are
trying to cover its software part.
Now lets come to the point i am working on my DIGITAL
LOGIC DESIGN lab we are using two softwares in that
lab one is XILINX and the other one is
PROTEUS.now as the end of the semester is
approaching.We have to propose a software based DLD project (basic)
for our final lab assesment.
now please suggest me 4 to 5 Software based projects(XILINX &
Proteus).
The Design of program must be done on proteus and verilog coding on
xilinx.
Kindly let me know if u need any other information
NOTE: You are just asked to give suggestions and kindly give easy suggestions and plz dont give suggestions those are easily avlble on internet
like fire alarm system traffic signal etc
i m asking suggestions from chegg experts just because i need a bit easy and unique project
REGARDS!
In: Electrical Engineering
Using the following VHDL code for an 8 bit adder, make the sum be displayed on the seven segment display of an Elbert V2 Spartan 3A FPGA Board.
VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity state_bit_adder is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
D : in
STD_LOGIC;
Enable : out
STD_LOGIC_vector (2 downto 0);
input: in
std_logic_vector(7 downto 0);
SUM: out
std_logic_vector(8 downto 0));
end state_bit_adder;
architecture Behavioral of state_bit_adder is
type statetype is (start, secondstate);
signal state, nextstate: statetype;
signal tempsum1, tempsum: STD_LOGIC_VECTOR (8 downto 0);
begin
Enable <= "110";
process(clk, reset)
begin
if(reset ='0') then
state <= start;
elsif rising_edge(clk) then
state <= nextstate;
end if;
end process;
process(state, input, D)
begin
case (state) is
when start =>
tempsum1 <= ('0'&input);
if (D = '0') then
nextstate <= secondstate;
end if;
when secondstate =>
tempsum <= ('0'&input);
if (D = '0') then
nextstate <= start;
end if;
end case;
end process;
SUM <= tempsum1 + tempsum;
End Behavioral;
Constraint File:
###Clock
NET "clk" LOC = P129 | IOSTANDARD = LVTTL | PERIOD = 12 MHz;
NET "D" CLOCK_DEDICATED_ROUTE = FALSE;
############Input push buttons
NET "reset" LOC = P80 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW =
FAST | PULLUP;
NET "D" LOC = P79 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST |
PULLUP;
###########output LED
NET "SUM[7]" LOC = P46 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =
FAST;
NET "SUM[6]" LOC = P47 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =
FAST;
NET "SUM[5]" LOC = P48 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =
FAST;
NET "SUM[4]" LOC = P49 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =
FAST;
NET "SUM[3]" LOC = P50 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =
FAST;
NET "SUM[2]" LOC = P51 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =
FAST;
NET "SUM[1]" LOC = P54 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =
FAST;
NET "SUM[0]" LOC = P55 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =
FAST;
NET "SUM[8]" LOC = P117 | IOSTANDARD = LVTTL | SLEW =
SLOW | DRIVE = 12;
NET "Enable[0]" LOC = P120 | IOSTANDARD = LVTTL | SLEW
= SLOW | DRIVE = 12;
NET "Enable[1]" LOC = P121 | IOSTANDARD = LVTTL |
DRIVE = 8;
NET "Enable[2]" LOC = P124 | IOSTANDARD = LVTTL |
DRIVE = 8;
#####################################################################################################
## DP Switches
#####################################################################################################
NET "input[0]" LOC = P70 | PULLUP | IOSTANDARD = LVTTL | SLEW =
FAST | DRIVE = 8;
NET "input[1]" LOC = P69 | PULLUP | IOSTANDARD = LVTTL | SLEW =
FAST | DRIVE = 8;
NET "input[2]" LOC = P68 | PULLUP | IOSTANDARD = LVTTL | SLEW =
FAST | DRIVE = 8;
NET "input[3]" LOC = P64 | PULLUP | IOSTANDARD = LVTTL | SLEW =
FAST | DRIVE = 8;
NET "input[4]" LOC = P63 | PULLUP | IOSTANDARD = LVTTL | SLEW =
FAST | DRIVE = 8;
NET "input[5]" LOC = P60 | PULLUP | IOSTANDARD = LVTTL | SLEW =
FAST | DRIVE = 8;
NET "input[6]" LOC = P59 | PULLUP | IOSTANDARD = LVTTL | SLEW =
FAST | DRIVE = 8;
NET "input[7]" LOC = P58 | PULLUP | IOSTANDARD = LVTTL | SLEW =
FAST | DRIVE = 8;
In: Electrical Engineering
Verilog code for Traffic light controller.
Need a block diagram, Verilog codes used with testbench, and the waveforms screen-prints.
In: Electrical Engineering
a. Signal conditioning circuits are used to process the output
signal from a sensor of a measurement system to be suitable for the
next stage of operation. Discuss any four of these processes.
(12Marks)
b. To eliminate short term fluctuation of signals and provide
smoother form of signal, low pass filters are use. Using a passive
low pass RC filer having R= 500Ω, and C=50mF, draw the frequency
response graph using a range of frequencies from ??=0.01rad/s to
??=1000 rad/s.
In: Electrical Engineering
In: Electrical Engineering
With a PSoC4 in PSoC creator:
Using 2 external buttons b0 and b1 to represent ‘0’ and ‘1’, design a sequence detector using C code in PSoC Creator to detect a pattern “1101”. The board LED lights up once, when the sequence “1101” occurs. Use a serial terminal (UART component and serial terminal emulator application) to display the sequence entered. Use the board button for the sequence detector reset.
In: Electrical Engineering
Determine the value, true or false, of each of the
following Boolean expressions,
assuming that the value of the variable count is 0 and the value of
the variable limit is
10. Give your answer as one of the values true or false.
a. (count == 0) && (limit < 20)
b. count == 0 && limit < 20
c. (limit > 20) || (count < 5)
d. !(count == 12)
e. (count == 1) && (x < y)
f. (count < 10) || (x < y)
g. !( ((count < 10) || (x < y)) && (count >= 0)
)
h. ((limit/count) > 7) || (limit < 20)
i. (limit < 20) || ((limit/count) > 7)
j. ((limit/count) > 7) && (limit < 0)
k. (limit < 0) && ((limit/count) > 7)
l. (5 && 7) + (!6)
Hi teacher this is true false statement please help me out with this thanks
In: Electrical Engineering
How do I calculate the steady-state pitch angle for the unity step input for the above system in matlab workspace?
In: Electrical Engineering
Discuss the direct steam engine system along with their advantages and disadvantages.
In: Electrical Engineering
Designa low-pass filter that reduces magnitude of H(jw) to 0.4
for the signal with 10(X+4)Hz.
a)Use 10 Ω resistor and calculate the value of the inductance of
the filter. Calculate the cutoff frequency of the filter
.b)Design another filter for the same purpose by using the same resistorcombined with a capacitor.Find the value of the capacitance.Find the magnitudes of H(jw) for 2Hz and 200 Hz frequencies and sketch the frequency response graph of the filter
c)(20+Y)Ωresistive loadis connected across the output terminals of the second filter. Find the new cutoff frequency (in hertz)of the loaded filter.Explain the effect of connecting load by considering the new cutoff frequency. Derive an expression for the new transfer function for the loaded cases.
X=6 Y=0
In: Electrical Engineering
Without using a Timer function, write a program to read the distance from the HC-SR04 ultrasonic sensor and display the distance on the C12832 lcd.
*please refer the HC-SR04 datasheet for the operation of the ultrasonic sensor, and mbed website for C12832 library and Timer function
In: Electrical Engineering
At time t = -250/6 μs a sinusoidal voltage is zero and is increasing. The next zero voltage takes place at t = 1250/6 μs and t = 0, it has a value equal to 75 V. This voltage is applied to an inductor, whose inductance is equal 0,0041 H
a) Write the instantaneous voltage equation.
b) The value, in module, of the inductor's reactance.
c) The phasor value of the effective current flowing through the circuit.
d) Draw the phasor diagram of the voltage and current.
e) If the frequency of the voltage signal is reduced in half, determine the modulus of the effective current flowing through the inductor.
In: Electrical Engineering
find 3 Different PLC’s and provide the details for each below I would suggest searching for 1 of each of the following PLC’s but you can use any 3 PLCs as long as they have different properties.
Different I/O properties Fixed I/O Modular I/O Different Manufactures
Allen Bradley
Automation Direct
Siemens
1. The first PLC found in the search CPU- (model number and manufacture)
Rack/Module format, (fixed or Number of slots)
Power Supply, (Power requirements)
Provide a Starting Address for each Input and Output
Input Modules:
Quanity
Type:
Voltage
Output Modules:
Quanity
Type:
Voltage
AMP rating
2.The second PLC found in the search
CPU- (model number and manufacture)
Rack/Module format, (fixed or Number of slots)
Power Supply, (Power requirements)
Provide a Starting Address for each Input and Output
Input Modules:
Quanity
Type:
Voltage
Output Modules:
Quanity
Type:
Voltage
AMP rating
The Third PLC found in the search
CPU- (model number and manufacture)
Rack/Module format, (fixed or Number of slots)
Power Supply, (Power requirements)
Provide a Starting Address for each Input and Output
Input Modules:
Quanity
Type:
Voltage
Output Modules:
Quanity
Type:
Voltage
AMP rating
In: Electrical Engineering