create a process flow diagram for the manufacturing of cell phones

Q01
h layers 2 and 3 of X.25. Are both necessary, or is this control mechanisms are used at bot-Flow .sredundant? Explain the problems which can be avoided for having flow control at both layer .

Question 1:

What is the main use of stepper motors?

What are the similarities and differences between a reluctance, a permanent magnet and hybrid stepper motors? Describe the construction of a hybrid stepper motor.

A signal with a maximum frequency of 3 kHz is sampled at 50 kHz. What would the required transition width be in Hertz to...
(a) decimate the signal by a factor of 8? (b) decimate the signal by a factor of 5? (c) interpolate the signal by a factor of 4?

Mention and explain the working principle of two types of one-shot!

1. For three resistors, R1, R2, and R3, sketch the schematic for the circuit if all three are connected in parallel and determine in general the equivalent resistance.

2. For three resistors, R1, R2, and R3, sketch the schematic for the circuit if all three are connected in series and determine in general the equivalent resistance.

3. What will the equivalent resistance be for three 300 Ohm resistors connected in parallel?

1.If an inverting voltage amplifier with a large gain were built to amplify a small sinusoidal
signal and the output waveform was observed to be sinusoidal but with a much lower
amplitude than predicted by a theoretical analysis assuming an ideal operational amplifier,
what non ideal property of the operational amplifier would be likely contributing to this
degradation in performance?
40

1. In a certain pint in an electrical system, the available fault current is 12 pu. Determine the actual fault current using a base power of 100 MVA and a base voltage of 34.5 kV

2. The positive, negative and zero sequence reactances of a 20 MVA, 13.2 kV synchronous generator are 0.3 pu, 0.2 pu and 0.1 pu respectively. The generator is solidly grounded and is not loaded. A line to ground fault occurs on phase a. Neglect all resistances, determine the fault current.

3. A 15 MVA, 34.5 kV/6.24 kV transformer is connected at an infinite bus. The percent impedance of the transformer is 2.5%. What is the current at the 34.5 kV side for a three phase short at the 6.24 kV side?

What are two major ways to reduce the phase‐to‐neutral capacitance of overhead transmission lines?
How does this compare to methods used to reduce line inductance?

Which circuit that controls the segments of a 7-segment display most represents a function in truth table form? mux, decoder, or minimal SOP?

Which (mux, decoder, or minimal SOP) most represent the circuit in sum of minterms form?

If required to quickly prototype a circuit for testing, which would you choose if the circuit were described using a truth table? (mux, decoder, or minimal SOP)

If creating a final design for mass production, which would you choose (mux, decoder, or minimal SOP) to implement a seven segment display and why?

QI/ True or False, correct the false if exist. 1- In SRM motors, reluctance torque is produced by the tendency of the rotot to move to its maximum reluctunce position 2- Hybrid stepping motors combine aspects of both permanent magnet and cupper winding technologies. 3. In Single-phase half-wave ac valtage controller, a single pulse is enough to operate the converter for a complete electrical cycle 360. 4 In single-phase cycloconverter, if there are 4 input electrical cycles then there have to he 2 tops and 2 bottoms in the output electrical cycle. 5- In Single-phase full-converter drives of DC motors, during regeneration for reversing the direction of power flow, the back emf of the motor can he reversed by reversing the field coil terminal connections. 6- In ac generators, regulating the rpm of the rotating magnetic field controls the magnitude of the voltage produced. 7- A regulated DC power supply cannot maintains the output voltage constant if there are fluctuations in ac mains or load variations. 8- A wound-rotor induction motor is designed to have a High-rotor resistunce so that the running efficiency is high and the full-load slip is low. 9- Mix phases operation mode of stepper motor is better than one phase operation 10- In power control of DC-DC converter drives, the dissipated in rheostat

It is required to design a synchronous sequential circuit that receives two input bit streams X and Y, and detects identical 4-bit sequences in both X and Y that are non-overlapping. The output Z is also a bit stream that produces a 1 only after detecting two identical 4-bit input sequences. Use an asynchronous reset input to reset the sequential circuit to its initial state.
Example:
X: 001010 110010 0111 1010100 0111
Y: 011010 100010 0111 1000100 0010
Z: 000001 000001 0001 0000001 0000
a) (5 points) Draw a Mealy state diagram of the sequential circuit.
b) (10 points) Implement your design using a minimal number of D-type flip flops and combinational logic. Show the K-maps and write the minimal next state and output equations. Draw the circuit diagram.
c) (10 points) Write a structural Verilog model that models your implemented sequential circuit by modeling the D Flip-Flops and instantiating them and modeling the combinational part using either assign statement or gate primitives.
d) (10 points) Write a test bench that tests your structural Verilog model in (c) using the given input sequence. Start by resetting all flip-flops and then apply the input sequences of X and Y shown above. Verify that your circuit produces the correct output by including the generated waveform from simulation.
e) (10 points) Write a behavioral Verilog description that models your state diagram in part (a).
f) (5 points) Write a test bench that tests your behavioral Verilog model of part (e). Start by resetting all flip-flops and then apply the input sequences of X and Y shown above. Verify that your circuit produces the correct output by including the generated waveform from simulation.
g) Submit a report (Word or PDF document) that should contain:
i. The state diagram of your design (part a).
ii. The K-maps, equations, and circuit diagram of your sequential circuit (part b).
iii. A copy of the Verilog modules and test benches of parts (c) to (f)
iv. The timing diagrams (waveforms) taken directly as snapshots from the simulator for
parts (d) and (f).
Take All the time you need.