Question

In Verilog, implement a circuit capable of adding and subtracting 8-bit binary numbers. You should submit a single Verilog file that contains all of the necessary modules and also contain a module named top(A, B, sel, F, C).

For the selection, use a 0 to select Addition and a 1 to select Subtraction.

Answer 1

// verilog code full adder

module full_adder (

input A,B,Cin,

output S,Cout);

  

assign S = (A ^ B ^ Cin);

assign Cout = ( A & B ) | ( B & Cin) | (A & Cin) ;

  

endmodule

//verilog code for exor gate

module xor_gate (

input A,B,

output Y );

  

assign Y = A ^ B ;

  

endmodule

//verilog code for 8 bit adder/subtractor module

module add_sub_8bit (

  

//input ports declarations

input [7:0] A,B,

input sel,

  

//output port declarations

output [7:0] F,

output C

);

  

  

//internal signal declarations

wire [7:0] x ;

wire [6:0] c ;

  

//instantiation of xor gates

xor_gate U0 ( sel , B[0] , x[0] );

xor_gate U1 ( sel , B[1] , x[1] );

xor_gate U2 ( sel , B[2] , x[2] );

xor_gate U3 ( sel , B[3] , x[3] );

xor_gate U4 ( sel , B[4] , x[4] );

xor_gate U5 ( sel , B[5] , x[5] );

xor_gate U6 ( sel , B[6] , x[6] );

xor_gate U7 ( sel , B[7] , x[7] );

  

//instantiaion of full adders

full_adder F0 ( A[0] , x[0] , sel , F[0] , c[0] );

full_adder F0 ( A[1] , x[1] , c[0] , F[1] , c[1] );

full_adder F0 ( A[2] , x[2] , c[1] , F[2] , c[2] );

full_adder F0 ( A[3] , x[3] , c[2] , F[3] , c[3] );

full_adder F0 ( A[4] , x[4] , c[3] , F[4] , c[4] );

full_adder F0 ( A[5] , x[5] , c[4] , F[5] , c[5] );

full_adder F0 ( A[6] , x[6] , c[5] , F[6] , c[6] );

full_adder F0 ( A[7] , x[7] , c[6] , F[7] , C );

  

  

endmodule

// verilog testbench code for 8 bit adder/subtractor

module test ;

  

reg [7:0] A,B;

reg sel;

  

wire [7:0] F;

wire C;

  

//instantiate UUT (unit under test)

add_sub_8bit UUT (.A(A),.B(B),.sel(sel),.F(F),.C(C));

  

//input stimulus generations

initial begin

$dumpfile ("waves.vcd");

$dumpvars;

A = 8'b00101101 ; B = 8'b00101101; sel = 1'b0; #10;

A = 8'b00100101 ; B = 8'b00100001; sel = 1'b1; #10;

A = 8'b00100001 ; B = 8'b00101101; sel = 1'b0; #10;

A = 8'b00100000 ; B = 8'b00100001; sel = 1'b1; #10;

A = 8'b10101101 ; B = 8'b00101101; sel = 1'b0; #10;

A = 8'b11101111 ; B = 8'b00100000; sel = 1'b1; #10;

$finish;

end

  

  

endmodule

// I verified design code with simulation and waveforms are attached below;