Flip Flop Inc. (FFI) has a capacity to manufacture up to 100,000 flip flops annually in...

Flip Flop Inc. (FFI) has a capacity to manufacture up to 100,000 flip flops annually in Canada. For next year, expected production and sales are 80,000 units with sale price of $10 per unit. The following costs are expected:

Production and sales	80,000 units
Direct materials used	120,000 $
Direct labour	80,000
MOH variable	120,000
MOH fixed	280,000
Selling expenses variable	64,000
Selling expenses fixed	56,000

FFI received the following offers:

1. Africa Imports (AI) would like to purchase 10,000 units for $8.70 $ sale price per unit.

2. China Imports (CI) would like to purchase 20,000 units for $6.60 sale price per unit.

There will be no selling expenses on AI and CI orders. There will be no impact on regular sales in Canada.

a) Calculate the impact on FFI operating income if AI order is accepted.

b) Calculate the impact on FFI operating income if CI order is accepted.

c) Which offer should FFI accept? Why?

d) For the offer you recommend in c) above, mention and explain two qualitative factors FFI should consider before making the final decision.

Expert Solution

ekkarill92 answered 7 months ago

Flip-flops: a) Make a asyncronous MOD 12 flip-flop up counter circuit b) Make a syncronous MOD...

Flip-flops: a) Make a asyncronous MOD 12 flip-flop up counter circuit b) Make a syncronous MOD 14 flip-flop up counter circuit c) Each flip-flop has the same propagation delay, which is 10ms. Calculate the maximum clock frequency of the circuit in questions (a) and (b)

Design a 5-bit binary counter using JK flip flops. Draw the flip-flop circuit diagram, the state...

Design a 5-bit binary counter using JK flip flops. Draw the flip-flop circuit diagram, the state graph, the timing diagram, the truth table (with clk pulse) and the state table (with present and next states).

Imagine a new kind of flip-flop called a J N flip-flop which has two inputs J...

Imagine a new kind of flip-flop called a J N flip-flop which has two inputs J and N. Input J behaves like the J input of the J K flip-flop, and input N behaves like the complement of the K input of a J K flip-flop (N=K’). Derive the characteristic table and excitation table of the J N flip-flop. Show that a D flip-flop can be constructed from a J N flip-flop by connecting its two inputs (J and N)...

Design up counter asyncronous MOD 12 and MOD 14 with JK Flip-Flop

Design a Count-up Counter in Aiken code with following flip flops: a) D-FF (Active edge is...

Design a Count-up Counter in Aiken code with following flip flops: a) D-FF (Active edge is high to low) b) SR-FF (Active edge is high to low) c) Use of output of circuit in part (b) and minimum number of logic gates for getting the Countdown counter in Aiken code

Implement the synchronous 2-bit Up/Down counter with saturation at the end states. The flip-flop outputs Q1,...

Implement the synchronous 2-bit Up/Down counter with saturation at the end states. The flip-flop outputs Q1, Q0 serve as the outputs of the counter. The counting direction is set with mode control input M. With M =1 the flip-flop outputs follow the incrementing binary sequence starting from a current state with saturation at state 11 as shown in the following example: 00-> 01-> 10-> 11-> 11-> 11... With M =0 the outputs follow the decrementing binary sequence from a current...

Design an up/down counter with four states (0, 1, 2, 3) using clocked JK flip flops....

Design an up/down counter with four states (0, 1, 2, 3) using clocked JK flip flops. A control signal x is used as follows: When x = 0 the machine counts forward (up), when x = 1, backward (down). Simulate using MultiSim and attach a simulation printout. Please address the following: State Table State Diagram Flip Flop Excitation Tables K-Map Simplification and Resulting Diagram MultiSim Simulation

Implement the synchronous 2-bit Up/Down counter with saturation at the end states. The flip-flop outputs Q1, Q0...

Implement the synchronous 2-bit Up/Down counter with saturation at the end states. The flip-flop outputs Q1, Q0 serve as the outputs of the counter. The counting direction is set with mode control input M. With M =1 the flip-flop outputs follow the incrementing binary sequence starting from a current state with saturation at state 11 as shown in the following example: 00-> 01-> 10-> 11-> 11-> 11... With M =0 the outputs follow the decrementing binary sequence from a current state...

A sequential circuit has two JK flip-flops A and B, two inputs r and y,...

A sequential circuit has two JK flip-flops A and B, two inputs r and y, and one output z. The flip-flop input equations and circuit output equation are $\begin{aligned} J_{A} &=A^{\prime} x+B^{\prime} y & K_{A}=B x^{\prime} y^{\prime} \\ J_{B} &=A^{\prime} x y & K_{B}=A^{\prime}+B^{\prime} x \\ z &=A^{\prime} x^{\prime}+B^{\prime} y^{\prime} & \end{aligned}$(a) Derive the simplified state equations for A and B. (b) Tabulate the state table. (c) Draw the state diagram of the çircuit.

Design a synchronous counter, using T flip-flops, that has the following sequence: 0010, 0110, 1000, 1001,...

Design a synchronous counter, using T flip-flops, that has the following sequence: 0010, 0110, 1000, 1001, 1100, 1101, and repeat. From the undesired states the counter must always go to 0010 on the next clock pulse.

Question