Question

Short Verilog Answers: a) (1 pt) What is the purpose of using “reg”? How different is it from “wire”? b) (1 pt) What do you mean by blocking and non-blocking statements in Verilog? How are assignments done in blocking and non-blocking statements? c) (2 pts) Given the logic circuit as follows, use Data Flow Modelling to design this circuit using Verilog.

Answer 1

a)  reg elements can be used as output within an actual module declaration. But, reg elements cannot be connected to the output port of a module instantiation. Thus, a reg can drive a wire as RHS of an assign statement. On the other way round, a wire can drive a reg in as RHS of a procedural block.

b)  Blocking Statements: A blocking statement must be executed before the execution of the statements that follow it in a sequential block. In the example below the first time statement to get executed is a = b followed by

Nonblocking Statements: Nonblocking statements allow you to schedule assignments without blocking the procedural flow. You can use the nonblocking procedural statement whenever you want to make several register assignments within the same time step without regard to order or dependence upon each other. It means that nonblocking statements resemble actual hardware more than blocking assignments.

Example - Blocking

  module blocking (clk,a,c); input clk; input a; output c; wire clk; wire a; reg c; reg b; always @ (posedge clk ) begin b = a; c = b; end endmodule

Example - Nonblocking

  module nonblocking (clk,a,c); input clk; input a; output c; wire clk; wire a; reg c; reg b; always @ (posedge clk ) begin b <= a; c <= b; end endmodule

Note :- please explain part c properly.