Question

Please try to solve all of them

True/false questions

1. T   F         A blocking assignment in Verilog is used to synchronize assignment statements so that they appear to execute at the same time.
2. T          F           A blocking assignment in Verilog completes execution before next statement executes.
3. T          F           Verilog Hardware description language is case sensitive.
4. T          F           An “if” statement must always be inside of an “always” block.
5. T          F           Verilog may be written at the Behavioral, Structural, Gate, Switch and Transistor levels.
6. T          F           Modules encapsulate design hierarchy, and communication with other modules through a set of declared input, output, and bidirectional ports.
7. T          F           A sequential UDP uses the values of its inputs and the current values of its output to determine the next value of its output.
8. T          F           The forever construct executes the loop a fixed number of times.
9. T          F           The explicit continuous assignment is a combined net and continuous assignment e.g. wire z1= x1 l x2.
10. T          F            Verilog behavior modeling models the circuit behavior without respect to any implementation or structure.
11. T          F            Verilog contains two structured procedure statements of behaviors: initial and always.
12. T          F            Verilog supports two types of assignments within always bock: Blocking and nonblocking assignments.

Answer 1

1 )

A blocking assignment in Verilog is used to synchronize assignment statements so that they appear to execute at the same time. -.TRUE

A time comes when the  blocking assignments occurs when the RHS variable of one assignment in one procedural block is also the LHS variable of another assignment in another procedural block and both equations are scheduled to execute in the same simulation time step, such as on the same clock edge. If blocking assignments are not properly ordered, a race condition can occur. When blocking assignments are scheduled to execute in the same time step

2 )

A blocking assignment in Verilog completes execution before next statement executes.- FALSE

because Blocking assignment statements in verilog are assigned using = and are executed one after the other in a procedural block means sequentially.

3.)

Verilog Hardware description language is case sensitive. - FALSE

because upper case letters are equivalent to lower case letters.

4.)

An “if” statement must always be inside of an “always” block - TRUE

5.)

Verilog may be written at the Behavioral, Structural, Gate, Switch and Transistor levels.- TRUE.

6.)

Modules encapsulate design hierarchy, and communication with other modules through a set of declared input, output, and bidirectional ports.- TRUE

because a Verilog design consists of a hierarchy of modules and modules are encapsulate design hierarchy, and communicate with other modules through a set of declared input, output, and bidirectional ports.

7.)

A sequential UDP uses the value of its inputs and the current value of its output to determine the next value of output.-TRUE

because the  Sequential UDPs provide an efficient and easy way to model sequential circuits such as latches and flip-flops.

8.)

The forever construct executes the loop a fixed number of times.-FASE because

The forever loop executes continually, the loop never ends. Normally we use forever statements in initial blocks. One should be very careful in using a forever statement: if no timing construct is present in the forever statement, simulation could hang

9.)

The explicit continuous assignment is a combined net and continuous assignment e.g. wire z1= x1 l x2.- TRUE they combined it in one statement.

10.)

Verilog behavior modeling models the circuit behavior without respect to any implementation or structure.-FALSE because it models with respect to any implementation or structure.

11.)

Verilog contains two structured procedure statements of behaviors: initial and always.-TRUE.

Initial blocks execute only once at time zero and always blocks loop toexecute over and over again,in other words as the same suggests it always executes.

11.)

Verilog supports two types of assignments within always bock: Blocking and nonblocking assignments- TRUE

Verilog supports two types of assignments within always blocks,with subtly different behaviours.

non-blocking assinment- in non blocking all assignments deffered untill all right hand sides have ebeen evaluted

and in blocking assignment - Evaluation and assignments are immediate .

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