Question

True/false questions

1. T          F           A hazard or glitch in digital logic is a fault in the logic system due to a change at the input.
2. T          F           A circuit with a hazard isn't a problem if the output values are allowed to settle to a steady state before being sampled.
3. T          F           The cause of hazards is the timing delay of different components in the circuit.
4. T          F           Adding delay can remove hazards, if one has good control of propagation delays.
5. T          F          A Verilog reg variable cannot be the output of a pre-defined primitive.
6. T          F          In Verilog nets & registers may be either scalars or vectors.
7. T          F           Verilog module may have at most five outputs.
8. T          F          Verilog permits module ports to be unconnected.
9. T          F          UDPs can have one or more scalar inputs, but only one scalar output.
10. T          F           The assignment symbol = is used to represent a nonblocking procedural assignment.
11. T          F           The assignment symbol >= is used to represent a nonblocking procedural assignment.
12. T          F         A blocking assignment in Verilog is used to synchronize assignment statements so that they appear to execute at the same time.
13. T         F           A blocking assignment in Verilog completes execution before next statement executes.
14. T          F           Verilog Hardware description language is case sensitive.
15. T          F           An “if” statement must always be inside of an “always” block.
16. T          F           Verilog may be written at the Behavioral, Structural, Gate, Switch and Transistor levels.
17. T          F           Modules encapsulate design hierarchy, and communication with other modules through a set of declared input, output, and bidirectional ports.
18. T          F           A sequential UDP uses the values of its inputs and the current values of its output to determine the next value of its output.
19. T          F           The forever construct executes the loop a fixed number of times.
20. T          F           The explicit continuous assignment is a combined net and continuous assignment e.g. wire z1= x1 l x2.
21. T          F            Verilog behavior modeling models the circuit behavior without respect to any implementation or structure.
22. T          F            Verilog contains two structured procedure statements of behaviors: initial and always.
23. T          F           Verilog supports two types of assignments within always bock: Blocking and nonblocking assignments.

Answer 1

Hi, i have tried to explain from my side as much as possible a and if still any doubt do comment.

I have tried solving as many as possible in time limit, please do repost others.

If you like my solution please rate the solution.

1) False because a hazard in a digital circuit is a temporary disturbance in ideal operation of the circuit which if given some time, gets resolved itself. These disturbances or fluctuations occur when different paths from the input to output have different delays and due to this fact, changes in input variables do not change the output instantly but do appear at output after a small delay caused by the circuit building elements, i.e., logic gates.

2) True

3) True

4) True, if you can manage delay then you can control over hazards.

6) True

The following example gives some examples of Verilog data types

wire net1;                  // single bit net 
reg r1;                  // single bit register 
tri [7:0] bus1;                  // 8 bit tristate bus 
reg [15:0] bus1;                  // 15 bit register 
reg [7:0] mem[0:127];                        // 8x128 memory register 
parameter state1 = 3'b001;                            // 3 bit constant 

7) False

8) True

If you don't need the output it's OK to leave it unconnected. If it's an input, you might want to connect it to a 0 or 1 as the case requires.

9) True, All UDP have exactly one output that can be either 0 , 1 or X and never Z (not supported).

10) False, non blocking assifnment is represented by <=.

11) False