Question

15. Approximately, how many NAND gate equivalents does a SPLD (Simple Programmable Logic Device), CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) typically support?

Answer 1

The size of a device is measured in how many equivalent two-input NAND gates it can represent. A SPLD or CPLD typically has about 20 equivalent gates per macrocell

SPLD NAND GATES Equivalents ::

SPLD i.e., construction of PAL with 8 macrocells is equivalent to 8*20 :: 160 gates

CPLD NAND GATES Equivalents ::

CPLD i.e., construction of PAL with 500 macrocells is equivalent to 500*20 = 10,000 gates

FPGA NAND GATES Equivalents ::

For multiple generations of HAPS systems Synopsys has used the following tried, true and field proven calculation as to ASIC gate equivalent capacity of the Xilinx FPGA families. The basis of the calculation is that you can map the equivalent of six two input NAND gates per Look Up Table, LUT per Logic Cell, LC.

1* LUT = 6 Two input NAND Gate equivalent

So its easy to calculate the total capacity of the FPGA in ASIC NAND Gate equivalent as you then multiply the LC count per FPGA by 6.

FPGA is used in Xilinx large devices used for Prototyping and details are added as following

• Xilinx Virtex-5 series biggest capacity device was listed as 330K LC’s, so 330K times 6 = 1,980,000 two input ASIC NAND gate equivalents (~2 million)

• Xilinx Virtex-6 = 760K LC’s = 4,560,000 two input ASIC NAND gate equivalents, (~4.5 million)
• Xilinx Virtex-7 = 2000K LC’s = 12,000,000 two input ASIC NAND gate equivalents, (~12 million)
• Xilinx UltraScale = 4400K LC’s = 26,400,000 two input ASIC NAND gate equivalents (~26.4 million)