Question

In: Electrical Engineering

Design a counter with an external control, x, to count the sequence of multiples of 3...

Design a counter with an external control, x, to count the sequence of multiples of 3 (i.e., 0-3-6 and repeat) when the control is 0, and non-multiples of 3 (i.e., 1-2-4-5-7 and repeat) when the control is 1. These values will be displayed on a seven-segment display. When the control value changes, the first clock should drive the output to the first value in the appropriate count- e.g., if the circuit has been counting non multiples and the control switches to 0, the first clock should drive the output to 0 (or if you have been counting multiples and the control switches to 1, the first clock pulse should make the output 1).

Solutions

Expert Solution

multisim simulation result of designed counter)


Related Solutions

Design a modified sequence counter (Student ID Counter) that will count out the following sequence: The...
Design a modified sequence counter (Student ID Counter) that will count out the following sequence: The first four unique digits in your StudentID (not including the digit 9) followed by the digit 9 and then repeat. Use the excitation table method for your design. Treat unused states as “don’t cares”. Include a switch to initialize the counter to the first count in your sequence. Your design should include the following: • a state diagram (include only the valid states) •...
Design a synchronous counter having the count sequence given by the following table. Use negative edge-triggered...
Design a synchronous counter having the count sequence given by the following table. Use negative edge-triggered T flip-flops provided with a clock. (i) Draw the state diagram of the counter. (ii) Build the counter's state table showing the synchronous inputs of the T flip-flops as well. (iii) Using Karnaugh maps, find the minimal sum-of-products form of the equations for the inputs to the flip-flops; assume the next states of the unused combinations to be "don't care states" (iv) Draw the...
Design a synchronous 3-bit binary counter that generates the repeated sequence of 0, 3, 4, 7,...
Design a synchronous 3-bit binary counter that generates the repeated sequence of 0, 3, 4, 7, 0, 3, 4, 7, 0… The outputs of the flip-flops are to be the binary output signals of your counter. Your solution needs to include the input equations for the flip-flops, and a circuit diagram for each version. a) Design the counter using D flip-flops b) Design the counter using T flip-flops c) Design the counter using JK flip-flops
A)  Design 0?379 count?up counter with BCD counter blocks if input clear signal is synchronous. B) Design...
A)  Design 0?379 count?up counter with BCD counter blocks if input clear signal is synchronous. B) Design 0?379 count?up counter with BCD counter blocks if input clear signal is Asynchronous. C) Design of 1/577 frequency divider with BCD count?up counters (Clear signal is Asynchronous)
Please write in multisim: Design 3 bit a synchronous counter to produce the following sequence: 0, 1, 2, 5, 3 then 0.by using...
Please write in multisim: Design 3 bit a synchronous counter to produce the following sequence: 0, 1, 2, 5, 3 then 0.by using J-K Filp Flop.. Please i need in multisim and Step of solution. Thanks!!
Write a Java loop statement that prints count. Count begins with 1. It increments as multiples...
Write a Java loop statement that prints count. Count begins with 1. It increments as multiples of 2 and does the loop until count is less than 50.
Design a Count-up Counter in Aiken code with following flip flops: a) D-FF (Active edge is...
Design a Count-up Counter in Aiken code with following flip flops: a) D-FF (Active edge is high to low) b) SR-FF (Active edge is high to low) c) Use of output of circuit in part (b) and minimum number of logic gates for getting the Countdown counter in Aiken code
design a sequence detector that detects the sequence: 110. The device has one input x and...
design a sequence detector that detects the sequence: 110. The device has one input x and one output Y. When the input sequence is set to 1 followed by a 1 followed by a 0, then Y is set to 1 otherwise Y is set to 0. Use J-K flip-flops and minimum number of states is designing this detector and show the followings: a) Show the state diagram b)Show the state table for this detector
(a) Design a 4-bit ring counter. Use an external asynchronous INIT input to initialize the flip-flops...
(a) Design a 4-bit ring counter. Use an external asynchronous INIT input to initialize the flip-flops to a valid initial state. Also remember to hook up the CLOCK to all flip-flops. (b) Design a 4-bit Johnson counter. Use an external asynchronous INIT input to initialize the flip-flops to a valid initial state. Also remember to hook up the CLOCK to all flip-flops. (c) How many states does the ring counter in part (a) have? How many states does the Johnson...
Create a 3-bit counter in verilog that cycles through this sequence, 6,2,4,5,0,7,3,1, with a synchronous rest...
Create a 3-bit counter in verilog that cycles through this sequence, 6,2,4,5,0,7,3,1, with a synchronous rest 4.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT