Question

Design a synchronous counter having the count sequence given by the following table. Use negative edge-triggered T flip-flops provided with a clock. (i) Draw the state diagram of the counter. (ii) Build the counter's state table showing the synchronous inputs of the T flip-flops as well. (iii) Using Karnaugh maps, find the minimal sum-of-products form of the equations for the inputs to the flip-flops; assume the next states of the unused combinations to be "don't care states" (iv) Draw the logic diagram of the counter

Q3 Q2 Q1 Q0
0 0 0 0
0 1 0 1
0 0 1 0
1 0 1 1
0 1 1 0
0 1 0 0
1 1 0 0
1 0 0 1
1 1 1 0

Answer 1

Here is the solution:

Circuit using negative edge triggered flipflops:

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