Question

1.)

A.) In a 5V system if you were asked to take one input HIGH and another LOW what would you do (i.e. where would you connect them)?

B.) If Vcc is 5.0V in CMOS logic, what are the acceptable high and low levels for the inputs?

C.) If Vcc is 5.0V in CMOS logic, what are the acceptable high and low levels for the outputs?

D.) You can directly connect any of the ICs from one logic family to another logic family (i.e. CMOS, TTL, LVTTL, HCMOS, etc.) together without concern that their input and output logic levels will be compatible: True or   False

E.) In any logic family would .25V be considered a logic low?    Yes or No

Answer 1

A) WE CAN SELECT EITHER CMOS OR TTL FOR THE CONNECTION BECAUSE BOTH CIRCUITS HAVE 5V HIGH INPUT IS ACCEPTABLE .

BUT FOR THE LOW INPUT LEVEL OF 5V WE HAVE NO SUCH LOGIC GATE FOR IT ..

ALL LOGIC GATES LIKE TTL - 0-0.8 V ,CMOS- 0-1.5V/0-3V/0-4V IS AVAILABLE

AND FOR 0-4V LOW LEVEL GATE THE HIGH LEVEL REQUIRED IS 15-11V.

SO IF WE DESIGHN FOR A GREATED ONE ONLY WE CAN ACCEPT A 5V LOW LEVEL GATE SIGHNAL..

B)

ACCEPTABLE CMOS INPUT HIGH SIGNAL LEVEL IS : 3.5-5.0 V

ACCEPTABLE CMOS INPUT LOW SIGNAL LEVEL IS : 1.5-0V

C)

ACCEPTABLE CMOS OUTPUT HIGH SIGNAL LEVEL IS : 4.95-5.0 V

ACCEPTABLE CMOS OUTPUT LOW SIGNAL LEVEL IS : 0.05-0V

D) TRUE

CMOS and TTL are the two most widely used logic families. Although ICs belonging to the same logic family have no special interface requirements, that is, the output of one can directly feed the input of the other, the same is not true if we have to interconnect digital ICs belonging to different logic families. Incompatibility of ICs belonging to different families mainly arises from different voltage levels and current requirements associated with LOW and HIGH logic states at the inputs and outputs.

E) YES

BOTH TTL AND CMOS HAVE THERE LOW LOGIC STATES LIES IN (TTL- 0-0.8V, CMOS- 0-1.5V)

SO BOTH CAN OPERATE IN LOW LOGIC STATE AT THIS INPUT

TTL gates operate on a nominal power supply voltage of 5 volts, +/- 0.25 volts. Ideally, a TTL “high” signal would be 5.00 volts exactly, and a TTL “low” signal 0.00 volts exactly. However, real TTL gate circuits cannot output such perfect voltage levels, and are designed to accept “high” and “low” signals deviating substantially from these ideal values. “Acceptable” input signal voltages range from 0 volts to 0.8 volts for a “low” logic state, and 2 volts to 5 volts for a “high” logic state. “Acceptable” output signal voltages (voltage levels guaranteed by the gate manufacturer over a specified range of load conditions) range from 0 volts to 0.5 volts for a “low” logic state, and 2.7 volts to 5 volts for a “high” logic state

CMOS gate circuits have input and output signal specifications that are quite different from TTL. For a CMOS gate operating at a power supply voltage of 5 volts, the acceptable input signal voltages range from 0 volts to 1.5 volts for a “low” logic state, and 3.5 volts to 5 volts for a “high” logic state. “Acceptable” output signal voltages (voltage levels guaranteed by the gate manufacturer over a specified range of load conditions) range from 0 volts to 0.05 volts for a “low” logic state, and 4.95 volts to 5 volts for a “high” logic state