Question

Use Verilog to design and implement a function as  c = c+∑b*ai, i is from 1 to 8. Here ai is stored in a SRAM with width as 16 and depth as 8 (8 rows of 16‐bit data), and b is stored in a 16‐bit register. c is initialized as 0.

Answer 1

the Verilog code for the following shown:

// Code your design here
module equation(c,clk);
reg [15:0] b=2;// register b
input clk;
output reg [31:0] c=0;
reg [31:0] temp=0;
reg [3:0] i=0;
reg [3:0] j;
reg [15:0] a [8];// RAM
initial// just used for initializng the Sram of A since no input is ataken from ports
begin
for(j=0;j<8;j++)
a[j]=j;
end
always@(posedge clk)
begin

if(i<8)
begin
//a_temp=a[i];
temp=a[i]*b+temp;
i=i+1;
end
else
begin
c=temp+c;
$display("c=%d",c);
i=0;
end
end
endmodule

testbench:

// Code your testbench here
// or browse Examples
module test();
wire [31:0] c;
reg clk;
equation e1(c,clk);
initial
begin
clk=0;
$dumpfile("dump.vcd");
$dumpvars(2);
#100 $finish;
end
initial
forever
#2 clk=~clk;
endmodule

waveform: