Question

Design and Test an 8-bit Adder using 4-bit adder. Use

4-bit adder coded in class using full adder that is coded using data flow model. Use test bench

to test 8-bit adder and consider at least five different test vectors to test it.

in behavioral not endmodule

plz help me

Answer 1

--VHDL top level CODE for 8 bit adder using two 4 bit adders

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--entity declaration for 8 bit adder

entity Adder_8bit is

Port ( A : in STD_LOGIC_VECTOR (7 downto 0);

B : in STD_LOGIC_VECTOR (7 downto 0);

Cin : in STD_LOGIC;

S : out STD_LOGIC_VECTOR (7 downto 0);

Cout : out STD_LOGIC);

end Adder_8bit;

--archiecture declaration for 8 bit adder

architecture Behavioral of Adder_8bit is

-- 4 bit Adder VHDL Code Component Decalaration

component Adder_4bit

Port ( A : in STD_LOGIC_VECTOR (3 downto 0);

B : in STD_LOGIC_VECTOR (3 downto 0);

Cin : in STD_LOGIC;

S : out STD_LOGIC_VECTOR (3 downto 0);

Cout : out STD_LOGIC);

end component;

-- Intermediate Carry siganl declaration

signal C1: STD_LOGIC;

begin

-- Port Mapping 4bit Adder with insatntiations

FA1_4: Adder_4bit port map( A(3 downto 0), B(3 downto 0), Cin, S(3 downto 0), C1);

FA2_4: Adder_4bit port map( A(7 downto 4), B(7 downto 4), C1, S(7 downto 4),Cout);

end Behavioral;

--VHDL code for 4 bit full adder using 1 bit full adders

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--entity declaration for 4 bit adder

entity Adder_4bit is

Port ( A : in STD_LOGIC_VECTOR (3 downto 0);

B : in STD_LOGIC_VECTOR (3 downto 0);

Cin : in STD_LOGIC;

S : out STD_LOGIC_VECTOR (3 downto 0);

Cout : out STD_LOGIC);

end Adder_4bit;

--architecture declaration for 4 bit adder

architecture Behavioral of Adder_4bit is

-- Full Adder VHDL Code Component Decalaration

component full_adder_vhdl_code

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

Cin : in STD_LOGIC;

S : out STD_LOGIC;

Cout : out STD_LOGIC);

end component;

-- Intermediate Carry declaration

signal c1,c2,c3: STD_LOGIC;

begin

-- Instantiating (Port Mapping) Full Adder 4 times

FA1: full_adder_vhdl_code port map( A(0), B(0), Cin, S(0), c1);

FA2: full_adder_vhdl_code port map( A(1), B(1), c1, S(1), c2);

FA3: full_adder_vhdl_code port map( A(2), B(2), c2, S(2), c3);

FA4: full_adder_vhdl_code port map( A(3), B(3), c3, S(3), Cout);

end Behavioral;

-- VHDL CODE for full adder

Library IEEE;

use IEEE.std_logic_1164.all;

--entity declrartion for full adder

entity full_adder_vhdl_code is

port(

A,B ,Cin: in std_logic;

S, Cout: out std_logic);

end full_adder_vhdl_code;

--architecture behavorial declaration for full adder

architecture behavioral of full_adder_vhdl_code is

begin

--sum logic

S<=A xor B xor Cin;

-- carry logic

Cout<=((A xor B) and Cin) or (A and B);

end behavioral;

-- VHDL testbench code for 8 bit adder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--entity declaartion for testbench

entity Adder_test is

end Adder_test;

--architecture declaration for testbench

architecture behavioral of Adder_test is

--component declaration for 8 bit adder

component Adder_8bit is

Port ( A : in STD_LOGIC_VECTOR (7 downto 0);

B : in STD_LOGIC_VECTOR (7 downto 0);

Cin : in STD_LOGIC;

S : out STD_LOGIC_VECTOR (7 downto 0);

Cout : out STD_LOGIC);

end component;

--inputs and output signals

signal A,B,S : std_logic_vector (7 downto 0);

signal Cin,Cout : std_logic;

begin

--instantiate UUT of 8 bit adder

DUT : Adder_8bit port map (A=>A,B=>B,Cin=>Cin,S=>S,Cout=>Cout);

  

--input stimulus geneartion

stim_proc:process

begin

A <= "10101010";

B <= "01010101";

Cin <= '0';

wait for 10 ns;

  

A <= "10100000";

B <= "00000101";

Cin <= '0';

wait for 10 ns;

A <= "00100100";

B <= "00010101";

Cin <= '0';

wait for 10 ns;

A <= "00000000";

B <= "11000101";

Cin <= '0';

wait for 10 ns;

  

A <= "00000111";

B <= "11000101";

Cin <= '1';

wait for 10 ns;

  

A <= "11111111";

B <= "01010000";

Cin <= '1';

wait ;

  

end process;

end behavioral;

-- simulation waveforms