In: Computer Science
Redo the previous problem, assuming a 2-way set associative cache. If a cache set is full and a block has to be removed to make room for another, remove the block that has been in cache the longest (FIFO).
2-Way Set Associative Cache
Number of blocks in cache = 8 = 23.
Number of blocks in Main memory = 4K = 212
Block size = 8 bytes = 23.
Cache access time = 22 ns
Page fault time = 300 ns.
a)
Main memory size = 212 * 23 = 215 so address = 15 bits
Number of sets in cache = 23 / 2 = 22
Byte offset = 3 bits (required to access each byte in the block)
Set offset = 2 bits (required to access each set in cache)
Tag = 15-2-3= 10 bits
Main Memory Address = Tag(10 bits) Set Offset (2 bits) Byte Offset(3 bits)
b)
Loop runs from 0x0 to 0x43 (67 in decimal)
Each block of memory contains 8 bytes. So first time miss will happen for starting address of block but subsequent 7 addresses will be hit. Please note that number of cache blocks are 8 divided into 4 sets. Each set will have two blocks.
If particular set is full then we remove the block in FIFO order.
Pass 1 of Loop
Main Memory Block |
Addresses | Cache (Set, Block) | Number of Misses | Number of Hits |
0 | 0x0 - 0x7 | 0, 0 | 1 | 7 |
1 | 0x8 - 0xF | 1, 0 | 1 | 7 |
2 | 0x10 - 0x17 | 2, 0 | 1 | 7 |
3 | 0x18 - 0x1F | 3, 0 | 1 | 7 |
4 | 0x20 - 0x27 | 0, 1 | 1 | 7 |
5 | 0x28 - 0x2F | 1, 1 | 1 | 7 |
6 | 0x30 - 0x37 | 2, 1 | 1 | 7 |
7 | 0x38 - 0x3F | 3, 1 | 1 | 7 |
8 | 0x40 - 0x43 | 0, 0 | 1 | 3 |
Pass 2 of Loop
Main Memory Block |
Addresses | Cache (Set, Block) | Number of Misses | Number of Hits |
0 | 0x0 - 0x7 | 0, 1 | 1 | 7 |
1 | 0x8 - 0xF | 1, 0 | 0 | 8 |
2 | 0x10 - 0x17 | 2, 0 | 0 | 8 |
3 | 0x18 - 0x1F | 3, 0 | 0 | 8 |
4 | 0x20 - 0x27 | 0, 0 | 1 | 7 |
5 | 0x28 - 0x2F | 1, 1 | 0 | 8 |
6 | 0x30 - 0x37 | 2, 1 | 0 | 8 |
7 | 0x38 - 0x3F | 3, 1 | 0 | 8 |
8 | 0x40 - 0x43 | 0, 1 | 1 | 3 |
Pass 3 of Loop
Main Memory Block |
Addresses | Cache (Set, Block) | Number of Misses | Number of Hits |
0 | 0x0 - 0x7 | 0, 0 | 1 | 7 |
1 | 0x8 - 0xF | 1, 0 | 0 | 8 |
2 | 0x10 - 0x17 | 2, 0 | 0 | 8 |
3 | 0x18 - 0x1F | 3, 0 | 0 | 8 |
4 | 0x20 - 0x27 | 0, 1 | 1 | 7 |
5 | 0x28 - 0x2F | 1, 1 | 0 | 8 |
6 | 0x30 - 0x37 | 2, 1 | 0 | 8 |
7 | 0x38 - 0x3F | 3, 1 | 0 | 8 |
8 | 0x40 - 0x43 | 0, 0 | 1 | 3 |
Pass 4 of Loop
Main Memory Block |
Addresses | Cache (Set, Block) | Number of Misses | Number of Hits |
0 | 0x0 - 0x7 | 0, 1 | 1 | 7 |
1 | 0x8 - 0xF | 1, 0 | 0 | 8 |
2 | 0x10 - 0x17 | 2, 0 | 0 | 8 |
3 | 0x18 - 0x1F | 3, 0 | 0 | 8 |
4 | 0x20 - 0x27 | 0, 0 | 1 | 7 |
5 | 0x28 - 0x2F | 1, 1 | 0 | 8 |
6 | 0x30 - 0x37 | 2, 1 | 0 | 8 |
7 | 0x38 - 0x3F | 3, 1 | 0 | 8 |
8 | 0x40 - 0x43 | 0, 1 | 1 | 3 |
So Hit ratio = Number of hits / total access (hit+miss)
= 254/272
= 0.94485 = 93.38%
c)
Effective access time = Hit rate * cache access time + miss rate * page fault time
= (254/272) * 22 + (18/272)*300
= 40.39 ns