In: Electrical Engineering
C: Postlab Section: Design Calculation
1. Show the state table of 4-Bit synchronous binary counters.
2. Derive the transition table for JK flip-flop.
3. Derive the logic equation using Karnaugh Map.
4. Draw the corresponding logic circuit.
5. Draw the timing diagram for the circuit.
6. By observation on the 3-bit and 4-bit counter circuit, you should see a pattern. Apply the pattern to construct a 5-bit counter without going through the 5 steps above.