Question

Consider the following hypothetical microprocessor. Assume this processor uses 32-bit instructions. Assume the 32 bits are composed of an opcode of 7 bits and an address of 25 bits. Answer the questions below.

1. What is the memory capacity (in Bytes)? Show your work and give your final answer in megabytes (MB).
   2. Consider the following address and data bus widths, and discuss their impact on system speed.
   1. Local address bus width of 32 bits, and a local data bus width of 8 bits.
   2. Local address bus width of 8 bits, and a local data bus width of 8 bits.

Answer 1

Instruction size = 32 bits

Opcode = 7 bits

Address = 25 bits

(a) Maximum addressable memory capacity = 2²⁵ Bytes = 32 Megabytes

(b) Impact on system speed with different specifications:

(i) Local address bus width = 32 bits

Local data bus width = 8 bits

-- As the local address bus width is 32 bits, so we can decode and use the entire address at once.

-- As the data bus width is 8 bits so 4 cycles are required to fetch 32 bit operand and access the memory.

(ii) Local address bus width = 8 bits

Local data bus width = 8 bits

-- As the address bus width is 8 bits so 4 cycles are required to fetch 32 bit instruction and access the memory.

-- As the data bus width is 8 bits so 4 cycles are required to fetch 32 bit operand and access the memory.

-- So, total 8 cycles are required to fetch the 32 bit data; 4 for address and the remaining 4 for data.

-- The memory interface will be complex due to these eight cycles.

Hope this helps.