Question

What is a TLB, what is stored in it, for what purpose it is used, and who manages it? Why the instruction cache and date cache require separate TLBs? What techniques are used to reduce the TLB miss penalty?

Answer 1

The answer to the question is given below.

TLB--->
Translation Lookaside Buffer is a memory cache, that stores recent translations of virtual memory to a physical address. It is used for fast retrieval of addresses. IT is a part of chip's Memory Management Unit(MMU)

What is stored in it.
It stores the recent translation of virtual memory to a physical address that is used for fast retrieval of memory.

Purpose of TLB
We know that cache is part of the main memory. So, if CPU generates an address and if it does not find it in the cache. Then it has to fetch the data from the main memory. So, this way two main memory cycles are needed.
Here comes the TLB. It uses the registers to store the page table entry. So, when CPU generates the address, and if find it in TLB and memory access time is very less. And if it's not in TLB then only one main memory cycle is needed.

So, it improves the memory access time for any address that CPU generates.

Who manages it
It is a part of the Hardware chip - Memory Management Unit(MMU)
So, MMU manages it.

Why the instruction cache and data cache require separate TLBs?
There is a simple difference between the instruction cache and the data cache.
Instruction is only fetched or read from memory
But data can be read from memory and write into memory.
For instruction cache, blocks are copied to cache from memory.
But for data cache, blocks can be copied from memory to cache and from the cache to memory.
That's why we require separate TLB's for both.


What techniques are used to reduce the TLB miss penalty?
There are a lot of technologies that help to improve TLB performance.
1. Supporting variable Size Pages
The idea is just instead of using a small page like 2KB , use huge page size like 2MB
This will reduce the TLB miss penalty.

2.Reducing TLB flushing overhead
if we reduce the TLB flushing overhead, this will lead to TLB miss penalty.

3. TLB Prefetching
Prefetching the data in TLB will lead to Reduce the TLB miss penalty.

So, these three techniques reduce the TLB miss penalty.