Question

create a VHDL program for the Truth Table below. Please make sure

to create your code for the simplified circuit.

A	B	C	Z
0	0	0	0
0	0	1	1
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	1
1	1	0	1
1	1	1	0

Answer 1

The design code and testbench code for your reference are added below

library IEEE;
use IEEE.std_logic_1164.all;

entity simplog is
port(
  a: in std_logic;
  b: in std_logic;
    c: in std_logic;

  z: out std_logic);
end simplog;

architecture dataflow of simplog is
begin
z<= ((not b)and a)or(b xor c);
end dataflow;

TESTBENCH:

-- Testbench for simplog gate
library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is
-- empty
end testbench;

architecture tb of testbench is

-- DUT component
component simplog is
port(
  a: in std_logic;
  b: in std_logic;
      c: in std_logic;

  z: out std_logic);
end component;

signal a_in, b_in,c_in, z_out: std_logic;

begin

  -- Connect DUT
  DUT: simplog port map(a_in, b_in,c_in,z_out);

  process
  begin
    a_in <= '0';
    b_in <= '0';
        c_in <= '0';

    wait for 1 ns;
    a_in <= '0';
    b_in <= '0';
        c_in <= '1';

    wait for 1 ns;
    
  
    a_in <= '0';
    b_in <= '1';
        c_in <= '0';

    wait for 1 ns;
    a_in <= '0';
    b_in <= '1';
        c_in <= '1';

    wait for 1 ns;

    a_in <= '1';
    b_in <= '0';
        c_in <= '0';

    wait for 1 ns;
    a_in <= '1';
    b_in <= '0';
        c_in <= '1';

    wait for 1 ns;

    a_in <= '1';
    b_in <= '1';
        c_in <= '0';

    wait for 1 ns;
    a_in <= '1';
    b_in <= '1';
        c_in <= '1';

wait for 1 ns;
  end process;
end tb;

Please try again as I have used the same tool as that of yours and its working fine in this tool as well ,so we are getting the required waveform.