Suppose some FSM has 3 inputs, internal Ready, external bus-grant Grant, and external bus-free Free signals,...

Suppose some FSM has 3 inputs, internal Ready, external bus-grant Grant, and external bus-free Free signals, as well as 2 outputs, bus-request Req and bus-lock Lock signals. Show its Moore-type state diagram, assuming that the FSM implements the following bus protocol: (1) initially, the FSM outputs Req = 0 and Lock = 0 and waits for both Ready and Free to be asserted; (2) After receiving Ready = 1 and Free = 1, the FSM outputs Req = 1 and Lock = 0 and waits for Grant to be asserted; (3) After receiving Grant = 1, provided that both Ready and Free still equal 1, the FSM outputs Req = 0 and Lock = 1 and waits for Ready to become 0; once Ready = 0, the FSM returns to step (1).
NOTE: Should Ready and/or Free become 0 while waiting for Grant = 1, the FSM returns to step (1). The FSM ignores the Grant input in steps (1) and (3), and it ignores the Free input in step (3).

Expert Solution

venereology answered 1 hour ago

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