Question

Please provide ALL documentation stated at the bottom (in bold) for each circuit

Description: Build and test the following circuits using gate-level modeling in Verilog HDL.

1. 3-input majority function.

2. Conditional inverter (see the table below: x - control input, y - data input). Do NOT use XOR gates for the implementation.

x	Output
0	y
1	y'

3. Two-input multiplexer (see the table below: x,y - data inputs, z - control input).

z	Output
0	x
1	y

4. 1-bit half adder.

5. 1-bit full adder by cascading two half adders.

6. 1-bit full adder directly (as in fig. 4.7 in the text).

7. 4-bit adder/subtractor with overflow detection by cascading four 1-bit full adders (see fig. 4.13 in the text). Use multiple bit variables (vectors) for the inputs and output (see 4-bit-adder.vl)

Requirements:

1. Create truth tables and use maps for simplification (not needed for circuits 5 and 7).
2. Create a module for each circuit, instantiate it in a test module and test it.
3. The hierarchical circuits (5 and 7) should use instances of their constituent modules.
4. For testing use  all combinations of input values and show the corresponding output for all circuits except for the 4-bit adder/subtractor.
5. No need to use all possible inputs for testing the 4-bit adder/subtractor. You may pick one positive number, one negative number and 0, and then add and subtract all combinations of two of them. Test also overflow situations and show the inputs/output both in binary and signed decimal.

Documentation:

***************Write a project report containing for each circuit:***************************

1. Short text description.
2. Truth table and map for the functions that can be simplified (not needed for the hierarchical implementations 5 and 7).
3. Gate level circuit diagram with components and wires labeled with the names as used in the Verilog code. Use block diagrams for the components of the hierarchical circuits.
4. HDL source code (included as text, not image).
5. Verilog output showing the test results as explained in the requirements.

Answer 1

1. 3-Input Majority Function

1 if a majority of the inputs are 1, 0 otherwise

A	B	C	Majority
0	0	0	0
0	0	1	0
0	1	0	0
0	1	1	1
1	0	0	0
1	0	1	1
1	1	0	1
1	1	1	1

2-level AND-OR implementation

1. An AND-gate for each row of the table with 1 in the output column

2. All inputs (A, B, C) wired to the inputs of each AND-gate

3. Each AND-gate output wired to an input of a single OR-gate

4. “Program” the inputs of each AND-gate to implement one min-term (row) of the table

1. Conditional Inverter :

     

1. 2-input multiplexer

X	A	B	Output
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	1
1	0	0	0
1	0	1	1
1	1	0	0
1	1	1	1

4. 1-bit half adder

A	B	Sum	Carry
0	0	0	0
1	0	1	0
0	1	1	0
1	1	0	1

5. 1 bit full adder by cascading 2 half adders

C	B	A	Sum	Carry
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

6. 1-bit full adder directly

C	B	A	Sum	Carry
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

7. 4-bit Adder-Subtractor with overflow detection

A0 A1 A2 A3 for A

B0 B1 B2 B3 for B

Example : Lets take two 3 bit numbers A=010 and B=011 and input them in the full adder with both values of control lines.

For K=0:

B0(exor)K=B0 and C0=K=0

Thus from first full adder

= A0+B0

= 0+1

= 1,

S0=1

C1=0

Similarly,

S1=0 with C2=1

S2=1 and C2=0

Thus,

A = 010 =2   

B = 011 = 3

Sum = 0101 = 5

For K=1

B0(exor)K=B0' and C0=k=1

Thus

S0=1 and C1=0

Similarly

S1=1 and C2=0

S3=1 and c3=1

Thus,  

A = 010 = 2

B = 011 = 3

Sum(Difference) = 1111 = -1