Question

comparision of 8T SRAM and 6T SRAM cells with simulation graphs ?

Answer 1

1. 6T SRAM cell

In the conventional 6T SRAM cell the condition of a non destructive read operation and a reliable write operation is fulfilled by appropriately sizing all the transistors in the SRAM cell. Sizing is done according to the cell ratio (CR) [6] and pull up ratio (PR) [6] of the transistor.

Access to the cell is enabled by the word line (WL in figure) which controls the two access transistors M5 and M6 which, in turn, control whether the cell should be connected to the bit lines: BL and BL bar [7]. They are used to transfer data for both read and write operations. Although it is not strictly necessary to have two bit lines, both the signal and its inverse are typically provided in order to improve noise margins.

2. 8T SRAM cell

In 8T SRAM cell read noise margin of the sram cell has been enhanced by isolating the read and write operation. The 8T SRAM cell consists of 8 transistors. Utilizing single-ended data access for read operations with an alternative 8T SRAM circuit structure [8] reduces the memory cell area overhead as compared to the 9T SRAM circuit.

The left sub-circuit of the 8T memory cell is a conventional 6T SRAM cell. The write operation is identical with the conventional 6T SRAM cell. An alternative communication channel that is composed of a read bitline and a transistor stack formed by M6,M7and M8 is used for reading the stored data from the cell.