In: Electrical Engineering
simulate the 7T SRAM in cadense tool.show the response of waveforms.
The 7T SRAM cell is almost similar to 6T SRAM cell, the only difference is having an extra NM4 transistor connected in series with PM0 & NM1.
NM4 transistor prevents the leakage of voltage from node P to ground by making itself OFF during read operation.
It has an extra word line (WLB) that is complement to the main word line (WL).
At the time of operation, both WL and WWL are turned ON and WLB is kept low.
The simulated diagram is shown below.
Now, the waveforms which will I given below, it will represent the transient and DC simulation for 7T SRAM memory cell.
Input waveform and output waveform are shown along with power dissipated during transient and DC analysis.
Dynamic power and static power dissipation are measured with the help of cadence virtuoso calculator.
For 7T SRAM cell the dynamic power dissipated is 5.45 micro W whereas for static power 18.15pW
The simulations are carried at 1.8 V and the operating temperature is 27° C.
Thank you : )