Question

Suppose that our 9-member MIPS core instruction subset is to be augmented to include the addiu instruction. Explain how just the control bits generated by the control unit must be expanded or modified to allow the addiu instruction to be executed on the single-cycle datapath. Indicate the proper setting for each of the bits generated by the control unit for an addiu instruction

Answer 1

Question is not clear even though i am giving the basic explanation of MIPS core instructions and ADDIU instruction basics.

Reply me to this answer for further assistance.

The MIPS has a 32 bit architecture, with 32 bit instructions, a 32 bit data word, and 32 bit addresses. It has 32 addressable internal registers requiring a 5 bit register address. Register 0 always has the the constant value 0. Addresses are for individual bytes (8 bits) but instructions must have addresses which are a multiple of 4. This is usually stated as “instructions must be word aligned in memory.”

ALU
Some arithmetic and logical instructions operate on one operand from a register and the other from a 16-bit immediate value in the instruction word. The immediate operand is treated as signed for the arithmetic and compare instructions, and treated as logical (zero-extended to register length) for the logical instructions.

ADDIU ==> Add Immediate Unsigned Word

ADDIU performs the same arithmetic operation but, does not trap on overflow.