Question

I need assistance with using Verilog to code the following:

The decoder needs attention. Its function is to take the 10‐bit input, and give three 4‐bit signals. The first 4‐bit signal should be the number of hundreds, the second 4‐bit signal should be the number of tens, and the final 4‐bit signal should be the number of units. In Verilog, these can be calculated simply using the numerical operators, specifically: Divide (/)  Modulus(%)

Given:

input[9:0] number

reg[3:0] numb_bcd0, numb_bcd1, numb_bcd2;

       numb_bcd0 = number % 4'd10; //units
       numb_bcd1 = (number / 4'd10) % 4'd10; //tenths
       numb_bcd2 = ... //hundredths

I am having trouble figuring out how to calculate the hundredths place for numb_bcd2; Thanks for the help!

Answer 1

design module:

// Code your design here
module decoder(number,bcd2,bcd1,bcd0);
input [9:0] number;
output reg [4:0] bcd2,bcd1,bcd0;
always@(*)
begin
bcd0=(number % 10);
bcd1=(number / 10)%10;
bcd2=(number/100)%10;// for 100 place u need to divide the number by100 and mod to by10
end
endmodule

//testbench

// Code your testbench here
// or browse Examples
module test();
reg [9:0] number;
wire [4:0] bcd2,bcd1,bcd0;
  
decoder d1(.*);
initial
begin
number=400;
#2 number=677;
#2 number=0;
#2 number=1000;
#2 number=344;
end
initial
$monitor("number=%d bcd2=%d bcd1=%d bcd0=%d",number,bcd2,bcd1,bcd0);
endmodule

output:

[2019-12-21 03:13:20 EST] iverilog '-Wall' '-g2012' design.sv testbench.sv && unbuffer vvp a.out
number= 400 bcd2= 4 bcd1= 0 bcd0= 0
number= 677 bcd2= 6 bcd1= 7 bcd0= 7
number= 0 bcd2= 0 bcd1= 0 bcd0= 0
number=1000 bcd2= 0 bcd1= 0 bcd0= 0
number= 344 bcd2= 3 bcd1= 4 bcd0= 4
Done