Question

In: Computer Science

Design and implement a special purpose system that allows access to doors 1 and 2 (D1...

Design and implement a special purpose system that allows access to doors 1 and 2 (D1 and D2 respectively) by persons who have been given a valid four-bit binary code. The code is entered using four switches: S1, S2, S3, and S4. Each valid switch can be set to 0 or 1. The system gives access to doors according to the following scheme:

  1. D1 if 0101 or 1110 is entered.
  2. D1 and D2 if 0111 is entered.
  3. D2 if 0100 is entered.

Provide a truth table and implement your circuit only using NOR gates. The correct implementation of this circuit should only have two layers of NOR gates.

Solutions

Expert Solution

Truth Table:

    S1

    S2

    S3

    S4

    D1

    D2

    0

    0

    0

    0

    0

    0

    0

    0

    0

    1

    0

    0

    0

    0

    1

    0

    0

    0

    0

    0

    1

    1

    0

    0

    0

    1

    0

    0

    0

    1

    0

    1

    0

    1

    1

    0

    0

    1

    1

    0

    0

    0

    0

    1

    1

    1

    1

    1

    1

    0

    0

    0

    0

    0

    1

    0

    0

    1

    0

    0

    1

    0

    1

    0

    0

    0

    1

    0

    1

    1

    0

    0

    1

    1

    0

    0

    0

    0

    1

    1

    0

    1

    0

    0

    1

    1

    1

    0

    1

    0

    1

    1

    1

    1

    0

    0

D1 (S1, S2, S3, S4) = ​ M (0, 1, 2, 3, 4, 6, 8, 9, 10, 11, 12, 13, 15)

The POS of D1 = S2(S1’+S4’)(S1+S4)(S1’+S3)(S1’+S2)

D2 (S1, S2, S3, S4) = ​ M (0, 1, 2, 3, 5, 6, 8, 9, 10, 11, 12, 13, 15)

The POS of D2 = S2(S3+S4’)(S3’+S4)S1’


The POS of D1 = S2(S1’+S4’)(S1+S4)(S1’+S3)(S1’+S2)
[D1']' = {[S2(S1’+S4’)(S1+S4)(S1’+S3)(S1’+S2)]'}'
D1 = {S2'+(S1’+S4’)'+(S1+S4)'+(S1’+S3)'+(S1’+S2)'}'
D1 = [S2'+(S1’+S4’)'+(S1+S4)'+(S1’+S3)'+(S1’+S2)']'

The POS of D2 = S2(S3+S4’)(S3’+S4)S1’
[D2']' = [{S2(S3+S4’)(S3’+S4)S1’}']'
D2 = [S2'+(S3+S4’)'+(S3’+S4)'+(S1')']'
D2 = [S2'+(S3+S4’)'+(S3’+S4)'+S1]'

Circuit only using NOR gates


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