Question

1. Describe the sequence of data flow events that must happen in any processor during a fetch cycle. [4 Marks]

2. Pipelining techniques suffers different types of hazards. Use examples to illustrate two of these hazards. [3 Marks]

3. For a computer architecture that supports interrupts by the I/O module, which implementation options exist for determining the source of the interrupt? Explain.

[3 Marks]

Suppose you were given the task of evaluating the evolution of the I/O module in an effort to come up with better design. Describe the major milestones that you would include in your report. [5 Marks]

Answer 1

1:Describe the sequence of data flow events that must happen in any processor during a fetch cycle.

Ans:The exact sequence of events during an instruction cycle depends on the design of the CPU. We can, however, indicate in general terms what must happen. Let us assume that a CPU that employs a memory address register (MAR), a memory buffer register (MBR), a program counter (PC), and an instruction register (IR).

Data flow in the Fetch Cycle

Figure shows the flow of data during this cycle. The PC contains the address of the next instruc­tion to be fetched. This address is moved to the MAR and placed on the address bus. The control unit requests a memory read, and the result is placed on the data bus and copied into the MBR and then moved to the IR. Meanwhile, the PC is incremented by 1 preparatory for the next fetch.

During the fetch stage, the address stored in the PC is copied into the memory address register (MAR) and then the PC is incremented in order to "point" to the memory address of the next instruction to be executed. The CPU then takes the instruction at the memory address described by the MAR and copies it into the memory data register (MDR). The MDR also acts as a two-way register that holds data fetched from memory or data waiting to be stored in memory (it is also known as the memory buffer register (MBR) because of this). Eventually, the instruction in the MDR is copied into the current instruction register (IR) which acts as a temporary holding ground for the instruction that has just been fetched from memory.

The fetch step is the same for each instruction:

1. The CPU sends the contents of the PC to the MAR and sends a read command on the address bus
2. In response to the read command (with address equal to PC), the memory returns the data stored at the memory location indicated by PC on the data bus
3. The CPU copies the data from the data bus into its MDR (also known as MBR; see section Role of components above)
4. A fraction of a second later, the CPU copies the data from the MDR to the instruction register for instruction decoding
5. The PC is incremented so that it points to the next instruction. This step prepares the CPU for the next cycle.

The control unit fetches the instruction's address from the memory unit.

2:Pipelining techniques suffers different types of hazards. Use examples to illustrate two of these hazards.

Ans:There are situations, called hazards, that prevent the next instruction in the instruction stream from being executing during its designated clock cycle. Hazards reduce the performance from the ideal speedup gained by pipelining.

There are three classes of hazards:

• Structural Hazards. They arise from resource conflicts when the hardware cannot support all possible combinations of instructions in simultaneous overlapped execution.
• Data Hazards. They arise when an instruction depends on the result of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline.
• Control Hazards.They arise from the pipelining of branches and other instructions that change the PC.

Hazards in pipelines can make it necessary to stall the pipeline. The processor can stall on different events:

A cache miss. A cache miss stalls all the instructions on pipeline both before and after the instruction causing the miss.
A hazard in pipeline. Eliminating a hazard often requires that some instructions in the pipeline to be allowed to proceed while others are delayed. When the instruction is stalled, all the instructions issued later than the stalled instruction are also stalled. Instructions issued earlier than the stalled instruction must continue, since otherwise the hazard will never clear.

Data hazards with example

Data hazards occur when instructions that exhibit data dependence modify data in different stages of a pipeline. Ignoring potential data hazards can result in race conditions (also termed race hazards). There are three situations in which a data hazard can occur:

1. read after write (RAW), a true dependency
2. write after read (WAR), an anti-dependency
3. write after write (WAW), an output dependency

Consider two instructions i1 and i2, with i1 occurring before i2 in program order.

Read after write (RAW)[edit]

(i2 tries to read a source before i1 writes to it) A read after write (RAW) data hazard refers to a situation where an instruction refers to a result that has not yet been calculated or retrieved. This can occur because even though an instruction is executed after a prior instruction, the prior instruction has been processed only partly through the pipeline.

For example:

i1. R2 <- R5 + R3
i2. R4 <- R2 + R3

The first instruction is calculating a value to be saved in register R2, and the second is going to use this value to compute a result for register R4. However, in a pipeline, when operands are fetched for the 2nd operation, the results from the first have not yet been saved, and hence a data dependency occurs.

A data dependency occurs with instruction i2, as it is dependent on the completion of instruction i1.

Write after read (WAR)[edit]

(i2 tries to write a destination before it is read by i1) A write after read (WAR) data hazard represents a problem with concurrent execution.

Structural Hazard with example

A structural hazard occurs when two (or more) instructions that are already in pipeline need the same resource. The result is that instruction must be executed in series rather than parallel for a portion of pipeline. Structural hazards are sometime referred to as resource hazards.

Example: A situation in which multiple instructions are ready to enter the execute instruction phase and there is a single ALU (Arithmetic Logic Unit). One solution to such resource hazard is to increase available resources, such as having multiple ports into main memory and multiple ALU (Arithmetic Logic Unit) units.