In: Computer Science
Consider the following sequence of instructions:
I1 sub f4, f4, f0
I2 div f3, f4, f0
I3 add f2, f5, f9
I4 add f0, f2, f3
I5 mult f9, f2, f3
Answer the following three questions.
A. List all the dependencies among the instructions.
B. Name the hazard (WAW, WAR, RAW) for each dependency.
C. Discuss which dependencies can be removed through register renaming.
BEFORE answering lets see what are WAW,WAR,RAW
Data hazards do occur when instructions those exhibit data dependence, modify data in different stages of a pipeline. Hazard cause delays in the pipeline. There are mainly 3 types of data hazards:
1) RAW (Read after Write)
2) WAR (Write after Read) [Anti-Data dependency]
3) WAW (Write after Write) [Output data dependency]
Let there be two instructions I and J, such that J follow I. so,
WAR and WAW hazards occur during the out-of-order execution of the instructions
now lets see the dependencies above
I1 sub f4, f4, f0
f4 <- f4 - f0
I2 div f3, f4, f0
f3 <- f4 / f0
I3 add f2, f5, f9
f2 <- f5 + f9
I4 add f0, f2, f3
f0 <- f2 + f3
I5 mult f9, f2, f3
f9 <- f2 * f3
I1 and I2 have a RAW dependency , what is I2 read f4 before I1 writes in f4
I1 and I4 have WAR dependency, if I4 writes in f0 before I1 reads it
I2 and I4 have WAR dependency
I2 and I5 have RAW depedency, if I5 reads f3 before I2 writes on it
I3 and I4 have RAW dependency
I3 and I5 have RAW dependency,
We don not have any WAW dependency, as no 2 instructions are writing simultaneoulsy on same register.
So option A, B have answered above, lets see option C
Register renaming is done to avoid WAR and WAW data hazards.
So here, we can see,dependencies having WAR hazards are
I1 and I4
I2 and I4
HOPE I HELPED YOU.