Questions
A 5th filter is described by the difference equation: 2y(n)=2 x(n)+7 x(n-1)+3 x(n-2)-8 x(n-3)+ x(n-4)-8 x(n-5)+7...

A 5th filter is described by the difference equation: 2y(n)=2 x(n)+7 x(n-1)+3 x(n-2)-8 x(n-3)+ x(n-4)-8 x(n-5)+7 y(n-1)-3 y(n-2)+5y(n-3)- y(n-4) Determine the frequency response. Plot the magnitude and the phase response of this filter. Consider the plot -π≤w≤π for 501 points. Describe the magnitude response (Low pass filter, High Pass filter, etc.) Determine the system stability. Determine the impulse response h(n). You may set the period to -100≤n≤100 Determine the unit step response for -100≤n≤100 . (Matlab)

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Study how to use D/A converter regarding DAC0800 Manual (answer typed please) Understand the manual

  1. Study how to use D/A converter regarding DAC0800 Manual (answer typed please)

    Understand the manual

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The following details are known about a 150 hp motor, 240 V, 500 rpm, dc shunt...

The following details are known about a 150 hp motor, 240 V, 500 rpm, dc shunt motor. Nominal full load current: 500 A Insulation class: H Weight: 3400 kg

Find

1.The total losses and efficiency at full load.

2.Calculate the approximate shunt filed exciting current if the shunt field causes 20% of the total losses.

3.Calculate the value of the armature resistance knowing that 50% of the total losses at full load are due to armature resistance.

4.With your calculated armature resistance, determine the counter-emf.

5.Determine the torque of the motor at full load.

6.The supply voltage is decreased to 200 V, approximate the speed at this supplied voltage.

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A baseband signal s(t)=8cos(2000t + 45)V, is wideband FM modulated with carrier amplitude of 40 volts....

A baseband signal s(t)=8cos(2000t + 45)V, is wideband FM modulated with carrier amplitude of 40 volts. The index of modulation is beta=3.

a. show the simplified equation of the wideband FM modulation

b. determine wideband FM power using Bessel function table

c. Calculate Kf in the wideband FM modulation equation.

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design an electro- pneumatic circuit with three cylinder output .the process will be in sequence the...

design an electro- pneumatic circuit with three cylinder output .the process will be in sequence the cylinder 1 extend , cylinder 2 then cylinder 3(using Timers). draw the pneumatic circuit including directional control valve and cylinders etc.. draw the electric circuit of pneumatic circuit including switches, relays , timer etc..

if possible include the conveyor motor in electric circuit.

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A) The order of first 3 harmonics on the output voltage of a controlled 3-phase rectifier...

A) The order of first 3 harmonics on the output voltage of a controlled 3-phase rectifier in CCM operations are;

B) The order of first 5 harmonics on the input current of a controlled 3-phase rectifier in CCM operations are;

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What are the Components of Analog and digital data Acquisition system, Draw and Explain through Block...

What are the Components of Analog and digital data Acquisition system, Draw and Explain through Block diagram?

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6. Explain Radar Bearing and Range Resolution

6. Explain Radar Bearing and Range Resolution

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write a matlab code to simulate fiber optics communication system on matlab simulink

write a matlab code to simulate fiber optics communication system on matlab simulink

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A balanced Y-connected load having an impedance of 60 - j45Ω/ϕ is connected in parallel with...

A balanced Y-connected load having an impedance of 60 - j45Ω/ϕ is connected in parallel with a balanced Δ-connected load having an impedance of 90√2∠45∘ Ω/ϕ. The paralleled loads are fed from a line having an impedance of 2 + j2Ω/ϕ. The magnitude of the line-to-line voltage of the Δ-load is 200√3 V.

Part A: Calculate the magnitude of the phase current in the Y-connected load.

Part B: Calculate the magnitude of the phase current in the Δ-connected load.

Part C: Calculate the magnitude of the current in the line feeding the loads.

Part D: Calculate the magnitude of the line voltage at the sending end of the line.

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what is the minimum number of wires required between two start/stop push button controls?

what is the minimum number of wires required between two start/stop push button controls?

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1- A 480-V, 60-Hz, delta connected, synchronous generator has a synchronous reactance of 0.5 ohm and...

1- A 480-V, 60-Hz, delta connected, synchronous generator has a synchronous reactance of 0.5 ohm and Its rated Line current is 100 A. if the generator is connected to a 480V grid

Draw the phasor diagram and find EA, delta angle and output power under the following conditions

a- The generator supply the rated current at 0.8 PF lagging.

b-The generator supply the rated current at 1.0 PF.

c- The generator supply the rated current at 0.8 PF leading.

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a.)    What do you understand by the term system automation? b.)    Why do you think that automation is...

a.)    What do you understand by the term system automation?

b.)    Why do you think that automation is important in our day to day activities – discuss

c.)     There is the fear that automation will replace human activities resulting in unemployment. Do you align with this assertion? Support you claim with relevant points

d.)    What is the difference between robotics and automation?

In: Electrical Engineering

module traffic(a, b,clk, reset, P1, P2, PL1, PL2, ind); input a,b; input clk; //g=100 y=010 r=001...

module traffic(a, b,clk, reset, P1, P2, PL1, PL2, ind);

input a,b;

input clk; //g=100 y=010 r=001

input reset; //g for pedes = 000 red = 111

input ind;

output[2:0] P1;

output[2:0] P2; // two roads

output[1:0] PL1; //Pl is pedestrian

output[1:0] PL2;

reg [2:0] P1;

reg [2:0] P2;

reg [1:0] PL1;

reg [1:0] PL2;

reg [2:0] sig;

always @(posedge clk, posedge reset)

if(reset)

begin

P1 <= 3'b100;

P2 <= 3'b001;

PL1 <= 3'b111;

PL2 <= 3'b000;

end

else begin

// pass the next_state to current_state;

sig <= sig + 1;

  

  

case(sig[2:0])

3'b000:begin

P1 <= 3'b100; //path 1 is greeen

P2 <= 3'b001; //path 2 is red

PL1 <= 3'b111;

PL2 <= 3'b000;

end

  

3'b001:begin

P1 <= 3'b010; //path 1 is yellow

P2 <= 3'b001; // path 2 is red

PL1 <= 3'b000;

PL2 <= 3'b111;

end

3'b010:begin

P1 <= 3'b001; //path 1 is red

P2 <= 3'b100; //path 2 is green

PL1 <= 3'b000;

PL2 <= 3'b111;

end

3'b011:begin

P1 <= 5'b001; //path 1 is red

P2 <= 5'b010; //path 2 is yellow

PL1 <= 3'b000;

PL2 <= 3'b111;

end

3'b100:begin

P1 <= 3'b001; //path 1 is red

P2 <= 3'b001; //path 3 is red

PL1 <= 3'b000;

PL2 <= 3'b000;

end

5'b11111:sig<= 6'b00000;

default:begin   

  

end

endcase

end

endmodule

Can anyone write a testbench for this in Verilog, ind means indicator.

In: Electrical Engineering

Derive the state diagram, state table, state assignment table, and logic network using D flip-flops for...

Derive the state diagram, state table, state assignment table, and logic network using D flip-flops for the following circuit:

A FSM has two input, w1 and w2, and an output z. The machine has to generate z=1 when the previous four values of w1 and w2 are the same; otherwise z=0. Overlapping patterns are allowed. An example of the desired behavior is:

w1: 0 1 1 0 1 1 1 0 0 0 1 1 0
w2: 1 1 1 0 1 0 1 0 0 0 1 1 1
z: 0 0 0 0 0 1 0 0 0 0 1 1 1

In: Electrical Engineering