1. A collector-modulated power has a supply voltage of 48V and an average collector current of 600 mA. Determine: a) the input power to the transmitter? b) the modulating signal power needed to produce 100% modulation?

2) …. receivers convert all incoming signals to a lower, fixed frequency.

3) List all the frequencies that emerge from a mixer that is fed with an incoming frequency of 107.1 MHz and another frequency of 96.4 MHz

4. What is the Image Frequency that results from the signal frequency and local oscillator frequency?

F_S = 90 MHz              F_LO = 100 MHz           F_IMAGE=?

5) List all the frequencies that emerge from a mixer that is fed with an incoming frequency of 107.1 MHz and another frequency of 96.4 MHz. Which frequency is normally filtered out in a modern receiver?

a) AM transmitters more commonly use low-level modulation, while FM transmitters more commonly use high-level modulation. True or False

b) Explain the basic elements of a Single Side Band (SSB). What element distinguishes it from a DSB transmitter?

c) As regulated by FCC law, what component is used to generate the carrier frequency of broadcast transmitters?

d) A …. uses a ROM look-up table to generate sinewaves or other signal types for carrier signal generation.

e) Explain the difference between a Class C amplifier and Class A-B amplifier.

6. What would you use to interface a balanced output to an unbalanced input?

Consider the "Successive Approximation" based ADC with a 5-bit converter and a voltage range of 0 to 5.0 volts. Show how it would approximate an incoming analog voltage value of 1.723 volts using a drawing of volts vs. discrete time steps associated with sampling. Show each approximation step (upper and lower bound voltage limits), show final A/D Output in Hex and show Vmin-max and the actual error in this approximation as a voltage and as a percentage of the actual voltage.

Project Summary

A company asks you to design a controller for a basketball machine that will indicate that a
player has won a game if they get a total of 3 points. There are two sensors in this machine. One
in the backboard and on the inside of the orange rim. If a player shoots a shot and the ball hits the
backboard and the ball goes through the rim, then the play will gain 1 point. If the player shoots
the ball and it doesn't hit the backboard and the ball just goes through the rim, then the play will
gain 2 points. If the player hits the backboard and the ball does not go through the rim, then the
player will lose 1 point. The total score can only go down to zero and cannot become negative. If
the ball does not go through the rim or hit backboard, then it will count as a no shot and nothing
will happen. Once the player scores three points, the game ends, and a light will indicate that the
player has won.

Deliverables
• You need to design TWO finite-state synchronous machines so that the company can
pick one that appears more suitable. However, you should pick your favorite and come up
with convincing arguments why you favor one design over the other. You, for example,
can build a Moore design and a Mealy design and compare them. You should use D flip
flops for your designs. Mixing different types of flip flops with different trigger edge
sensitivity is possible but not recommended. Note that two designs which differ by only
the type of flip flop (e.g., J-K vs. D) or number of states (i.e., changing the type of FF or
inserting more unnecessary states) is not considered conceptually different.

1. A testbench is provided in the following directory (~lab_work/verification/task3) without the Device Under Test (DUT).(see testbench below)

`timescale 1ns/10ps

module tb_detector ;

reg clk, rst, datain;
wire det;

detector DUT ( .clk(clk), .rst(rst), .datain(datain), .det(det) );


initial
begin
#0 clk = 0;
datain = 0;
forever #5 clk = ~clk;
end

initial
begin
#0 rst = 0;
@ (negedge clk);
@ (negedge clk);
rst = 1;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 1;

@(posedge clk)
#2 if (det == 1)
$display ("det = %b, correct output", det);
else
$display ("det = %b, incorrect output", det);

@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 0;

@(posedge clk)
#2 if (det == 0)
$display ("det = %b, correct output", det);
else
$display ("det = %b, incorrect output", det);

@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 1;

@(posedge clk)
#2 if (det == 1)
$display ("det = %b, correct output", det);
else
$display ("det = %b, incorrect output", det);

@ (negedge clk);
datain = 1;

#100 $finish;
end



endmodule

2. Write a verilog code for the DUT that will do the following:

i) receive clk, rst dan datain signals from the provided testbench

ii) reset the output signal to LOW synchronously with the positive (rising) edge of clk when rst is set LOW

iii) produce an output signal similar to datain when rst is HIGH and the output transition occurs at the negative (falling) edge of clk.

3. Verify the design using the testbench.

1) Identify what are the factors and impacts that will influence the electricity demand growth rate.

Minimize the function with K-Map- F(A,B,C,D)= ПM(0,2,4,5,6,7,9,12).d(3,14)   

Design full adder with 4:1 MUX gates

1) What is the minimum value of random samples generated by the following MATLAB code?: 5*(2*rand-1)

2) What is the mean value of random samples generated by the following MATLAB code?:  3*randn-2

3) What is the mean value of random samples generated by the following MATLAB code?: 5*(2*rand-1)

Problem 8 ( please write neatly and in full )

a) Draw the block diagram with feed-forward. What are its advantages?
b) Why are limiters used and what are their effects?
c) What is the integrator windup and how can it be avoided?

A 500-kV, 60 Hz, three-phase completely transposed overhead line has three ASCR 1113-kcmil conductors per bundle, with 0.5 m between conductors in the bundle. The horizontal phase spacing between bundle centers are 10, 10, and 20 m. With a length of 190 km, the line delivers 1800 MW at 475 kV and at 0.90 power factor leading to the receiving end at full load. Using the nominal π circuit, calculate the: (a) ABCD parameters, (b) sending-end voltage and current, (c) sending-end power and power factor, and (d) the full load line losses and efficiency. Assume a 50 ̊C conductor temperature to determine the resistance of this line.

Problem 8 ( please answer neatly )

a) Draw the dc-motor equivalent circuit and its representation in Laplace domain. Is
this representation linear?
b) What is the transfer function of a proportional-integral (PI) controller?
c) Draw the block diagram of the torque loop.

Problem 8 ( please answer neatly )

i) What are the various blocks of a motor drive?
ii) What is a cascaded control, and what are its advantages?
iii) Draw the average models of a PWM controller and a dc-dc converter.

i need a design for a robot to be placed in swimming pools that detects drowning , in case drowning is detected it will automatically inflate an airbag to rescue the swimmer NOTE we need a design without using cameras and image processing the robot will be in the swimming pool