Hello guys

i would to build a buck converter and use arduino PWM to control the output voltage

12V to 8.4V

any ideas ?

thanks

Design Task 2: One Second Prescalar In many systems it is desirable to have a very fast system clock to clock most of the sequential entities in the system. However, there may be other sequential entities in the same system that need to be clocked at a much slower speed. An approach that allows flexibility in generating a slower clock frequency is a frequency divider, also called a prescalar. This is basically a counter that generates a pulse every n cycles of its input clock. The output occurs as a pulse with a frequency that is 1/n of the input clock frequency. However, the output pulse has a fixed duration that is one clk period long. 4 The prescalar to be designed is named one_sec_prescalar. If its cnt_en input is asserted at a rate of 32.768 kHz it must generate an output pulse every second. So, this design divides down it input by 32768. The input pulse is one system clock in duration and output pulse is one system clock in duration. This entity must also generate an output named one_hz that is a 1Hz square wave. The entity declaration for the one second prescalar is:

entity one_sec_prescalar is port( clk : in std_logic; -- system clock

rst_n : in std_logic; -- active low synchronous reset

clr_n : in std_logic; -- synchronous clear

cnt_en : in std_logic; -- count enable

one_hz : out std_logic; -- one Hz square wave output

one_sec_tick : out std_logic -- one clock wide pulse every sec );

How are the memory requirements for the real-time digital signal processing system affected by the sampling frequency, f s ? For example, if f s is increased by a factor of 2, what affect does this have on the system memory requirements?

(a) What is a high impedance relay and when is it used?

(b) A motor with differential protection has a full load current of 200 A. When starting, the motor takes 5 × FL current. The motor is remote from the switchgear which houses one set of CTs and the relay. If the CT ratios are 200/1, the secondary winding resistance is 1.0 ohm and the protection loop lead resistance to the motor is 6 ohms, calculate the minimum relay setting voltage. State what the CT knee point voltage should be.

Design sequential circuit for detect 11011 sequence using D flip flops clearly indicating the procedure and relevant diagrams. Write vrilog code for your circuit.

Step by step answers please.

Design a Digital Voting Machine using microcontroller based device which can be performed in election electronic voting system. (You can allow five candidates and 50 users. The overall result of the election should be displayed after all.)

Create an algorithm to design a solution

Write a programme to implement the given specification selecting an appropriate microcontroller. (Use Assembly or C languages)

Please attach schematic diagrams (Circuit diagram).

1a. Write your Verilog program to implement the timer counter. HEX0 should show tenths of seconds from 0 to 9. HEX1 and HEX2 should show a count of seconds, from 00 to 59. The ones count is on HEX1 and the tens count is on HEX2.

1b. Count backwards and forwards. Add a button or switch to control counting direction. When counting forwards or backwards, your count should not stop but rollover appropriately at the correct time. When counting forward, at 59.9, the count should roll over to 00.0. When counting backwards at 00.0, the count should roll back to 59.9.

1c.Add a preset signal. Preset should set the display count to 59. 9. Use a button for the preset.

1d.Employ a start/stop switch for the counter. When the switch is in the stop position, the count should not be updated on the seven segment displays. The displays should not be turned off, but should maintain the last count shown when the count is stopped. Example: count is 42.3 and the switch is set to stop count. The hex display should show 42.3. When the switch is placed in the start position, the count should resume from where it stopped.

So far I have code for the following: a divide by 2 clock, divide by 5 clock, divide by 10 clock, a decimal counter (0-9), and have started this last top level. However, do not know how to finish it. Please help me. Thanks!

module divide_by_2(Clk,reset, D, Q); //Divide by 2 clock with reset using D flip flop
  
   input wire Clk, D, reset;
   output wire Q;
  
   reg Qnext;
  
   assign Q = Qnext;
  
   always @(posedge Clk, posedge reset) //always at the positive edge of the clock or reset
       if (reset)
           begin // asynchronous reset when reset is high
           Qnext <= 1'b0;; //Q gets the value 0
           end
  
       else
           begin
           Qnext <= D; // Q gets the value of D on posedge of clock
           end
          
endmodule

module divide_by_5(Clk,reset,DA,DB,DC,DD,QA,QB,QC,QD,Y);

input wire DA,DB,DC,DD,Clk,reset;
output wire QA,QB,QC,QD,Y;

assign Y= QD | QB;

divide_by_2 inst0(Clk,reset,(~QA & ~QC),QA);
divide_by_2 inst1(Clk,reset,((QA & ~QB)|(~QA & QB)),QB);
divide_by_2 inst2(Clk,reset,(QA & QB),QC);
divide_by_2_Inverse inst3(Clk,reset,QB,QD);

endmodule

module divide_by_10(Clk_in, Clk_out, reset);

input Clk_in, reset;
output Clk_out;

divide_by_2 inst0(Clk_in,reset, Clk_in, Q);
divide_by_5 inst1(~Q,reset,QA,QB,QC,QD,QA,QB,QC,QD,Y);

assign Clk_out= Y;

endmodule

module decimal_counter(OVERFLOW, CLK, RST,A);  
   input CLK,RST;
   output OVERFLOW;
   output [3:0] A;
  
   reg OVERFLOW_reg;
   reg[3:0]A_reg;
  
   assign OVERFLOW = OVERFLOW_reg;
   assign A = A_reg;
  
   always @ (posedge CLK or negedge RST)
  
   //asynchronous reset condition takes priority check for that event first
   if (RST == 1'd0) begin  
       OVERFLOW_reg <= 1'b0;
       A_reg <= 4'b0000;
       end
   else if (A_reg < 4'd9)
       begin
       // as long as A is less than 9, add 1 to A
           A_reg <= A_reg + 1'b1;
       // do not trigger overflow because count A is still a single digit
           OVERFLOW_reg <= 1'b0;
       end
   else
       begin
       // Count A is double digit 10 here, reset count to 0
       // trigger overflow for the digit 1 that should be carried output
           A_reg <= 4'b0000;
           OVERFLOW_reg <= 1'b1;
       end
      
endmodule

module TopLevel(CLOCK_50, KEY, LEDR, HEX0, HEX1, HEX2);

input wire CLOCK_50;
input wire [2:0]KEY;
output wire [5:0]LEDR;
output wire [6:0]HEX0;

   reg [6:0]rHEX0;
   reg [6:0]rHEX1;
   reg [6:0]rHEX2;
  
   assign HEX0 = rHEX0;
   assign HEX1= rHEX1;
   assign HEX2= rHEX2;
  
   /* (OVERFLOW, CLK, RST,A)*/
   decimal_counter inst0(HEX2,CLOCK_50,KEY[1],HEX0);
   divide_by_5 inst1(Clk,KEY[1],A,DB,DC,DD,QA,QB,QC,QD,HEX1);
   decimal_counter inst2(HEX1,CLOCK_50,KEY[1],HEX2);
  
   always @(HEX0,HEX1)
  
   begin
  
   case (A)
       1'b0: rHEX0 = 7'h40;
       1'b1: rHEX0 = 7'h79;
       1'b2: rHEX0 = 7'h24;
       1'b3: rHEX0 = 7'h30;
       1'b4: rHEX0 = 7'h19;
       1'b5: rHEX0 = 7'h12;
       1'b6: rHEX0 = 7'h02;
       1'b7: rHEX0 = 7'h78;
       1'b8: rHEX0 = 7'h00;
       1'b9: rHEX0 = 7'h18;
   endcase
   end
  
   always @ (HEX2)
  
   begin
  
   case (A)
       1'b0: rHEX2 = 7'h40;
       1'b1: rHEX2 = 7'h79;
       1'b2: rHEX2 = 7'h24;
       1'b3: rHEX2 = 7'h30;
       1'b4: rHEX2 = 7'h19;
       1'b5: rHEX2 = 7'h12;
   endcase
   end

endmodule

In order for a dc motor to function properly, it must be protected from physical damage during the starting period. At starting conditions, the motor is not rotating, and armature generated voltage EA = 0 V. Since the internal resistance of a normal DC motor is very low, a very high current flows. It is possible for a motor to be severely damaged by such currents, even if they last for only a moment. A solution to the problem of excess current during starting condition is to insert a starting resistor in series with the armature to limit the current flow until EA can build up to its rating value. This starting resistor must not be in the circuit permanently, because it would result in excessive losses and would cause the motor's torque-speed characteristic to drop off excessively with an increase in load. In modern practice, a starting resistor is made up of a series of pieces, each of which is removed from the motor circuit in succession as the motor speeds up, in order to limit the current in the motor to a safe value. In this design problem, an automatic starter circuit is to be designed for a 4-point shunt motor rated at 15-hp, 240-V, and 45-A. The armature resistance of the motor is (0.5 + 0.XX) Ohm, and the shunt field resistance is (120 + Y) Ohm. The motor is to start with no more than (150 + Y) percent of its rated armature current, and as soon as the current falls to its rated value, the starting resistor stage must be cut out. Draw a neat diagram of a 4-point dc shunt motor starter. Determine the number of steps required in the starter and the value of the resistors in each step?

Please explain and give an example for each of the following:

What is the relationship between the FFT of a signal and the length of the sinewave, i.e. the number of samples?

What is the relationship between the FFT of a signal and the frequency of the sine wave?

What the region of main spectral energy is

A series-connected dc motor is designed to operate with a variable load. The resistances RA and RF are negligible. To attain high efficiency, the motor has been designed to have very small rotational losses. For a load torque of 80 N?m , the machine runs at its maximum rated speed of 1300 rpm . Find the speed for a load torque of 350 N?m

Make a write up on how a stepper motor control works. The Do's and Dont's. The motor is driven by TTL logic used to implement the controller. Use a 555 timer circuit to operate the controller at 3Hz. Write up to be 4-5 pages.

After the PICmicro code has been written, compiled, assembled and linked, what tools in the MPLAB IDE is most useful in determining the correctness and completion of your code?

1. Generate a sine wave with frequency 100 Hz.

a. Sample the signal with a sampling frequency (i) 1000 Hz and (ii) 1050 Hz.

b. For each frequency in Question 1(a), perform DFT for ONE (1) cycle and ONE and a HALF (1.5) cycles of the waveform. Comment on your observation.